diff options
| -rw-r--r-- | src/soc/intel/tigerlake/bootblock/pch.c | 11 |
1 files changed, 5 insertions, 6 deletions
diff --git a/src/soc/intel/tigerlake/bootblock/pch.c b/src/soc/intel/tigerlake/bootblock/pch.c index e9b11767ae..9fc5ce167b 100644 --- a/src/soc/intel/tigerlake/bootblock/pch.c +++ b/src/soc/intel/tigerlake/bootblock/pch.c @@ -50,22 +50,21 @@ static void soc_config_pwrmbase(void) { uint32_t reg32; + uint16_t reg16; /* * Assign Resources to PWRMBASE * Clear BIT 1-2 Command Register */ - reg32 = pci_read_config32(PCH_DEV_PMC, PCI_COMMAND); - reg32 &= ~(PCI_COMMAND_MEMORY); - pci_write_config32(PCH_DEV_PMC, PCI_COMMAND, reg32); + reg16 = pci_read_config16(PCH_DEV_PMC, PCI_COMMAND); + reg16 &= ~(PCI_COMMAND_MEMORY); + pci_write_config16(PCH_DEV_PMC, PCI_COMMAND, reg16); /* Program PWRM Base */ pci_write_config32(PCH_DEV_PMC, PWRMBASE, PCH_PWRM_BASE_ADDRESS); /* Enable Bus Master and MMIO Space */ - reg32 = pci_read_config32(PCH_DEV_PMC, PCI_COMMAND); - reg32 |= PCI_COMMAND_MEMORY; - pci_write_config32(PCH_DEV_PMC, PCI_COMMAND, reg32); + pci_or_config16(PCH_DEV_PMC, PCI_COMMAND, PCI_COMMAND_MEMORY); /* Enable PWRM in PMC */ reg32 = read32((void *)(PCH_PWRM_BASE_ADDRESS + ACTL)); |