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-rw-r--r--src/include/device/pci_ids.h2
-rw-r--r--src/soc/intel/cannonlake/bootblock/report_platform.c2
-rw-r--r--src/soc/intel/common/block/graphics/graphics.c2
3 files changed, 6 insertions, 0 deletions
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h
index 434449ccba..3da7410016 100644
--- a/src/include/device/pci_ids.h
+++ b/src/include/device/pci_ids.h
@@ -3925,7 +3925,9 @@
#define PCI_DID_INTEL_CML_GT1_ULT_3 0x9B2B
#define PCI_DID_INTEL_CML_GT1_ULT_4 0x9B2C
#define PCI_DID_INTEL_CML_GT2_ULT_5 0x9BAA
+#define PCI_DID_INTEL_CML_GT2_ULT_8 0x9BAC
#define PCI_DID_INTEL_CML_GT2_ULT_6 0x9BCA
+#define PCI_DID_INTEL_CML_GT2_ULT_7 0x9BCC
#define PCI_DID_INTEL_CML_GT2_ULT_3 0x9B4B
#define PCI_DID_INTEL_CML_GT2_ULT_4 0x9B4C
#define PCI_DID_INTEL_CML_GT1_ULX_1 0x9B20
diff --git a/src/soc/intel/cannonlake/bootblock/report_platform.c b/src/soc/intel/cannonlake/bootblock/report_platform.c
index c168431b03..fe362719c7 100644
--- a/src/soc/intel/cannonlake/bootblock/report_platform.c
+++ b/src/soc/intel/cannonlake/bootblock/report_platform.c
@@ -140,6 +140,8 @@ static struct {
{ PCI_DID_INTEL_CML_GT2_ULT_4, "CometLake ULT GT2" },
{ PCI_DID_INTEL_CML_GT2_ULT_5, "CometLake ULT GT2" },
{ PCI_DID_INTEL_CML_GT2_ULT_6, "CometLake ULT GT2" },
+ { PCI_DID_INTEL_CML_GT2_ULT_7, "CometLake ULT GT2" },
+ { PCI_DID_INTEL_CML_GT2_ULT_8, "CometLake ULT GT2" },
{ PCI_DID_INTEL_CML_GT1_ULX_1, "CometLake ULX GT1" },
{ PCI_DID_INTEL_CML_GT2_ULX_1, "CometLake ULX GT2" },
{ PCI_DID_INTEL_CML_GT1_S_1, "CometLake S GT1" },
diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c
index 30fc2c287b..98d19813a9 100644
--- a/src/soc/intel/common/block/graphics/graphics.c
+++ b/src/soc/intel/common/block/graphics/graphics.c
@@ -247,6 +247,8 @@ static const unsigned short pci_device_ids[] = {
PCI_DID_INTEL_CML_GT1_ULT_4,
PCI_DID_INTEL_CML_GT2_ULT_5,
PCI_DID_INTEL_CML_GT2_ULT_6,
+ PCI_DID_INTEL_CML_GT2_ULT_7,
+ PCI_DID_INTEL_CML_GT2_ULT_8,
PCI_DID_INTEL_CML_GT2_ULT_3,
PCI_DID_INTEL_CML_GT2_ULT_4,
PCI_DID_INTEL_CML_GT1_ULX_1,