diff options
-rw-r--r-- | src/soc/amd/stoneyridge/chip.c | 27 | ||||
-rw-r--r-- | src/soc/amd/stoneyridge/gpio.c | 10 |
2 files changed, 37 insertions, 0 deletions
diff --git a/src/soc/amd/stoneyridge/chip.c b/src/soc/amd/stoneyridge/chip.c index 3d82c37099..d447ffa8ab 100644 --- a/src/soc/amd/stoneyridge/chip.c +++ b/src/soc/amd/stoneyridge/chip.c @@ -22,6 +22,7 @@ #include <device/pci.h> #include <soc/cpu.h> #include <soc/northbridge.h> +#include <soc/pci_devs.h> #include <soc/southbridge.h> #include <amdblocks/psp.h> #include <amdblocks/agesawrapper.h> @@ -35,12 +36,38 @@ struct device_operations cpu_bus_ops = { .acpi_fill_ssdt_generator = generate_cpu_entries, }; +static const char *soc_acpi_name(const struct device *dev) +{ + if (dev->path.type == DEVICE_PATH_DOMAIN) + return "PCI0"; + if (dev->path.type != DEVICE_PATH_PCI) + return NULL; + + switch (dev->path.pci.devfn) { + case EHCI1_DEVFN: + return "EHC0"; + case LPC_DEVFN: + return "LPCB"; + case SATA_DEVFN: + return "STCR"; + case SD_DEVFN: + return "SDCN"; + case SMBUS_DEVFN: + return "SBUS"; + case XHCI_DEVFN: + return "XHC0"; + default: + return NULL; + } +}; + struct device_operations pci_domain_ops = { .read_resources = domain_read_resources, .set_resources = domain_set_resources, .enable_resources = domain_enable_resources, .scan_bus = pci_domain_scan_bus, .ops_pci_bus = pci_bus_default_ops, + .acpi_name = soc_acpi_name, }; static void enable_dev(device_t dev) diff --git a/src/soc/amd/stoneyridge/gpio.c b/src/soc/amd/stoneyridge/gpio.c index 86655fceb4..62edcd31a4 100644 --- a/src/soc/amd/stoneyridge/gpio.c +++ b/src/soc/amd/stoneyridge/gpio.c @@ -96,3 +96,13 @@ void gpio_output(gpio_t gpio_num, int value) reg |= GPIO_OUTPUT_ENABLE; write32((void *)(uintptr_t)gpio_num, reg); } + +const char *gpio_acpi_path(gpio_t gpio) +{ + return "\\SB.GPIO"; +} + +uint16_t gpio_acpi_pin(gpio_t gpio) +{ + return gpio; +} |