diff options
| -rw-r--r-- | src/soc/mediatek/mt8186/include/soc/spm.h | 533 |
1 files changed, 533 insertions, 0 deletions
diff --git a/src/soc/mediatek/mt8186/include/soc/spm.h b/src/soc/mediatek/mt8186/include/soc/spm.h new file mode 100644 index 0000000000..5ab11eafd9 --- /dev/null +++ b/src/soc/mediatek/mt8186/include/soc/spm.h @@ -0,0 +1,533 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on MT8186 Functional Specification + * Chapter number: 3.5 + */ + +#ifndef SOC_MEDIATEK_MT8186_SPM_H +#define SOC_MEDIATEK_MT8186_SPM_H + +#include <soc/addressmap.h> +#include <types.h> + +struct mtk_spm_regs { + uint32_t poweron_config_en; + uint32_t spm_power_on_val0; + uint32_t spm_power_on_val1; + uint32_t spm_clk_con; + uint32_t spm_clk_settle; + uint32_t spm_ap_standby_con; + uint32_t pcm_con0; + uint32_t pcm_con1; + uint32_t spm_power_on_val2; + uint32_t spm_power_on_val3; + uint32_t pcm_reg_data_ini; + uint32_t pcm_pwr_io_en; + uint32_t pcm_timer_val; + uint32_t pcm_wdt_val; + uint8_t reserved0[8]; + uint32_t spm_sw_rst_con; + uint32_t spm_sw_rst_con_set; + uint32_t spm_sw_rst_con_clr; + uint32_t spm_src6_mask; + uint8_t reserved1[52]; + uint32_t md32_clk_con; + uint32_t spm_sram_rsv_con; + uint32_t spm_swint; + uint32_t spm_swint_set; + uint32_t spm_swint_clr; + uint32_t spm_scp_mailbox; + uint32_t scp_spm_mailbox; + uint32_t spm_wakeup_event_sens; + uint32_t spm_wakeup_event_clear; + uint8_t reserved2[4]; + uint32_t spm_scp_irq; + uint32_t spm_cpu_wakeup_event; + uint32_t spm_irq_mask; + uint32_t spm_src_req; + uint32_t spm_src_mask; + uint32_t spm_src2_mask; + uint32_t spm_src3_mask; + uint32_t spm_src4_mask; + uint32_t spm_src5_mask; + uint32_t spm_wakeup_event_mask; + uint32_t spm_wakeup_event_ext_mask; + uint32_t spm_src7_mask; + uint32_t scp_clk_con; + uint32_t pcm_debug_con; + uint8_t reserved3[4]; + uint32_t ddren_dbc_con; + uint32_t spm_resource_ack_con4; + uint32_t spm_resource_ack_con0; + uint32_t spm_resource_ack_con1; + uint32_t spm_resource_ack_con2; + uint32_t spm_resource_ack_con3; + uint32_t pcm_reg0_data; + uint32_t pcm_reg2_data; + uint32_t pcm_reg6_data; + uint32_t pcm_reg7_data; + uint32_t pcm_reg13_data; + uint32_t src_req_sta_0; + uint32_t src_req_sta_1; + uint32_t src_req_sta_2; + uint32_t pcm_timer_out; + uint32_t pcm_wdt_out; + uint32_t spm_irq_sta; + uint32_t src_req_sta_4; + uint32_t md32pcm_wakeup_sta; + uint32_t md32pcm_event_sta; + uint32_t spm_wakeup_sta; + uint32_t spm_wakeup_ext_sta; + uint32_t spm_wakeup_misc; + uint32_t mm_dvfs_halt; + uint8_t reserved4[8]; + uint32_t bus_protect_rdy; + uint32_t bus_protect1_rdy; + uint32_t bus_protect2_rdy; + uint32_t bus_protect3_rdy; + uint32_t subsys_idle_sta; + uint32_t pcm_sta; + uint32_t src_req_sta_3; + uint32_t pwr_status; + uint32_t pwr_status_2nd; + uint32_t cpu_pwr_status; + uint32_t other_pwr_status; + uint32_t spm_vtcxo_event_count_sta; + uint32_t spm_infra_event_count_sta; + uint32_t spm_vrf18_event_count_sta; + uint32_t spm_apsrc_event_count_sta; + uint32_t spm_ddren_event_count_sta; + uint32_t md32pcm_sta; + uint32_t md32pcm_pc; + uint8_t reserved5[12]; + uint32_t dvfsrc_event_sta; + uint32_t bus_protect4_rdy; + uint32_t bus_protect5_rdy; + uint32_t bus_protect6_rdy; + uint32_t bus_protect7_rdy; + uint32_t bus_protect8_rdy; + uint8_t reserved6[20]; + uint32_t spm_twam_last_sta0; + uint32_t spm_twam_last_sta1; + uint32_t spm_twam_last_sta2; + uint32_t spm_twam_last_sta3; + uint32_t spm_twam_curr_sta0; + uint32_t spm_twam_curr_sta1; + uint32_t spm_twam_curr_sta2; + uint32_t spm_twam_curr_sta3; + uint32_t spm_twam_timer_out; + uint32_t spm_cg_check_sta; + uint32_t spm_dvfs_sta; + uint32_t spm_dvfs_opp_sta; + uint32_t spm_mcusys_pwr_con; + uint32_t spm_cputop_pwr_con; + uint32_t spm_cpu0_pwr_con; + uint32_t spm_cpu1_pwr_con; + uint32_t spm_cpu2_pwr_con; + uint32_t spm_cpu3_pwr_con; + uint32_t spm_cpu4_pwr_con; + uint32_t spm_cpu5_pwr_con; + uint32_t spm_cpu6_pwr_con; + uint32_t spm_cpu7_pwr_con; + uint8_t reserved7[4]; + uint32_t armpll_clk_con; + uint32_t mcusys_idle_sta; + uint32_t gic_wakeup_sta; + uint32_t cpu_spare_con; + uint32_t cpu_spare_con_set; + uint32_t cpu_spare_con_clr; + uint32_t armpll_clk_sel; + uint32_t ext_int_wakeup_req; + uint32_t ext_int_wakeup_req_set; + uint32_t ext_int_wakeup_req_clr; + uint8_t reserved8[12]; + uint32_t cpu_irq_mask; + uint32_t cpu_irq_mask_set; + uint32_t cpu_irq_mask_clr; + uint8_t reserved9[20]; + uint32_t cpu_wfi_en; + uint32_t cpu_wfi_en_set; + uint32_t cpu_wfi_en_clr; + uint8_t reserved10[20]; + uint32_t root_cputop_addr; + uint32_t root_core_addr; + uint8_t reserved11[40]; + uint32_t spm2sw_mailbox_0; + uint32_t spm2sw_mailbox_1; + uint32_t spm2sw_mailbox_2; + uint32_t spm2sw_mailbox_3; + uint32_t sw2spm_wakeup; + uint32_t sw2spm_wakeup_set; + uint32_t sw2spm_wakeup_clr; + uint32_t sw2spm_mailbox_0; + uint32_t sw2spm_mailbox_1; + uint32_t sw2spm_mailbox_2; + uint32_t sw2spm_mailbox_3; + uint32_t sw2spm_cfg; + uint32_t md1_pwr_con; + uint32_t conn_pwr_con; + uint32_t mfg0_pwr_con; + uint32_t mfg1_pwr_con; + uint32_t mfg2_pwr_con; + uint32_t mfg3_pwr_con; + uint32_t mfg4_pwr_con; + uint32_t mfg5_pwr_con; + uint32_t mfg6_pwr_con; + uint32_t ifr_pwr_con; + uint32_t ifr_sub_pwr_con; + uint32_t dpy_pwr_con; + uint32_t dramc_md32_pwr_con; + uint32_t isp_pwr_con; + uint32_t isp2_pwr_con; + uint32_t ipe_pwr_con; + uint32_t vde_pwr_con; + uint32_t vde2_pwr_con; + uint32_t ven_pwr_con; + uint32_t ven_core1_pwr_con; + uint32_t mdp_pwr_con; + uint32_t dis_pwr_con; + uint32_t audio_pwr_con; + uint32_t cam_pwr_con; + uint32_t cam_rawa_pwr_con; + uint32_t cam_rawb_pwr_con; + uint32_t cam_rawc_pwr_con; + uint32_t sysram_con; + uint32_t sysrom_con; + uint32_t sspm_sram_con; + uint32_t scp_sram_con; + uint32_t dpy_shu_sram_con; + uint32_t ufs_sram_con; + uint32_t devapc_ifr_sram_con; + uint32_t devapc_subifr_sram_con; + uint32_t devapc_acp_sram_con; + uint32_t usb_sram_con; + uint32_t dummy_sram_con; + uint32_t md_ext_buck_iso_con; + uint32_t ext_buck_iso; + uint32_t dxcc_sram_con; + uint32_t msdc_pwr_con; + uint32_t debugtop_sram_con; + uint32_t dp_tx_pwr_con; + uint32_t dpmaif_sram_con; + uint32_t dpy_shu2_sram_con; + uint32_t dramc_mcu2_sram_con; + uint32_t dramc_mcu_sram_con; + uint32_t mcupm_pwr_con; + uint32_t dpy2_pwr_con; + uint32_t spm_sram_con; + uint8_t reserved12[4]; + uint32_t peri_pwr_con; + uint32_t nna0_pwr_con; + uint32_t nna1_pwr_con; + uint32_t nna2_pwr_con; + uint32_t nna_pwr_con; + uint32_t adsp_pwr_con; + uint32_t dpy_sram_con; + uint32_t nna3_pwr_con; + uint8_t reserved13[8]; + uint32_t wpe_pwr_con; + uint8_t reserved14[4]; + uint32_t spm_mem_ck_sel; + uint32_t spm_bus_protect_mask_b; + uint32_t spm_bus_protect1_mask_b; + uint32_t spm_bus_protect2_mask_b; + uint32_t spm_bus_protect3_mask_b; + uint32_t spm_bus_protect4_mask_b; + uint32_t spm_emi_bw_mode; + uint32_t ap2md_peer_wakeup; + uint32_t ulposc_con; + uint32_t spm2mm_con; + uint32_t spm_bus_protect5_mask_b; + uint32_t spm2mcupm_con; + uint32_t ap_mdsrc_req; + uint32_t spm2emi_enter_ulpm; + uint32_t spm2md_dvfs_con; + uint32_t md2spm_dvfs_con; + uint32_t spm_bus_protect6_mask_b; + uint32_t spm_bus_protect7_mask_b; + uint32_t spm_bus_protect8_mask_b; + uint32_t spm_pll_con; + uint32_t rc_spm_ctrl; + uint32_t spm_dram_mcu_sw_con_0; + uint32_t spm_dram_mcu_sw_con_1; + uint32_t spm_dram_mcu_sw_con_2; + uint32_t spm_dram_mcu_sw_con_3; + uint32_t spm_dram_mcu_sw_con_4; + uint32_t spm_dram_mcu_sta_0; + uint32_t spm_dram_mcu_sta_1; + uint32_t spm_dram_mcu_sta_2; + uint32_t spm_dram_mcu_sw_sel_0; + uint32_t relay_dvfs_level; + uint8_t reserved15[4]; + uint32_t dramc_dpy_clk_sw_con_0; + uint32_t dramc_dpy_clk_sw_con_1; + uint32_t dramc_dpy_clk_sw_con_2; + uint32_t dramc_dpy_clk_sw_con_3; + uint32_t dramc_dpy_clk_sw_sel_0; + uint32_t dramc_dpy_clk_sw_sel_1; + uint32_t dramc_dpy_clk_sw_sel_2; + uint32_t dramc_dpy_clk_sw_sel_3; + uint32_t dramc_dpy_clk_spm_con; + uint32_t spm_dvfs_level; + uint32_t spm_cirq_con; + uint32_t spm_dvfs_misc; + uint8_t reserved16[4]; + uint32_t rg_module_sw_cg_0_mask_req_0; + uint32_t rg_module_sw_cg_0_mask_req_1; + uint32_t rg_module_sw_cg_0_mask_req_2; + uint32_t rg_module_sw_cg_1_mask_req_0; + uint32_t rg_module_sw_cg_1_mask_req_1; + uint32_t rg_module_sw_cg_1_mask_req_2; + uint32_t rg_module_sw_cg_2_mask_req_0; + uint32_t rg_module_sw_cg_2_mask_req_1; + uint32_t rg_module_sw_cg_2_mask_req_2; + uint32_t rg_module_sw_cg_3_mask_req_0; + uint32_t rg_module_sw_cg_3_mask_req_1; + uint32_t rg_module_sw_cg_3_mask_req_2; + uint32_t pwr_status_mask_req_0; + uint32_t pwr_status_mask_req_1; + uint32_t pwr_status_mask_req_2; + uint32_t spm_cg_check_con; + uint32_t spm_src_rdy_sta; + uint32_t spm_dvs_dfs_level; + uint32_t spm_force_dvfs; + uint8_t reserved17[256]; + uint32_t spm_sw_flag_0; + uint32_t spm_sw_debug_0; + uint32_t spm_sw_flag_1; + uint32_t spm_sw_debug_1; + uint32_t spm_sw_rsv_0; + uint32_t spm_sw_rsv_1; + uint32_t spm_sw_rsv_2; + uint32_t spm_sw_rsv_3; + uint32_t spm_sw_rsv_4; + uint32_t spm_sw_rsv_5; + uint32_t spm_sw_rsv_6; + uint32_t spm_sw_rsv_7; + uint32_t spm_sw_rsv_8; + uint32_t spm_bk_wake_event; + uint32_t spm_bk_vtcxo_dur; + uint32_t spm_bk_wake_misc; + uint32_t spm_bk_pcm_timer; + uint8_t reserved18[12]; + uint32_t spm_rsv_con_0; + uint32_t spm_rsv_con_1; + uint32_t spm_rsv_sta_0; + uint32_t spm_rsv_sta_1; + uint32_t spm_spare_con; + uint32_t spm_spare_con_set; + uint32_t spm_spare_con_clr; + uint32_t spm_cross_wake_m00_req; + uint32_t spm_cross_wake_m01_req; + uint32_t spm_cross_wake_m02_req; + uint32_t spm_cross_wake_m03_req; + uint32_t scp_vcore_level; + uint32_t sc_mm_ck_sel_con; + uint32_t spare_ack_mask; + uint32_t spm_spare_function; + uint32_t spm_dv_con_0; + uint32_t spm_dv_con_1; + uint32_t spm_dv_sta; + uint32_t conn_xowcn_debug_en; + uint32_t spm_sema_m0; + uint32_t spm_sema_m1; + uint32_t spm_sema_m2; + uint32_t spm_sema_m3; + uint32_t spm_sema_m4; + uint32_t spm_sema_m5; + uint32_t spm_sema_m6; + uint32_t spm_sema_m7; + uint32_t spm2adsp_mailbox; + uint32_t adsp2spm_mailbox; + uint32_t spm_adsp_irq; + uint32_t spm_md32_irq; + uint32_t spm2pmcu_mailbox_0; + uint32_t spm2pmcu_mailbox_1; + uint32_t spm2pmcu_mailbox_2; + uint32_t spm2pmcu_mailbox_3; + uint32_t pmcu2spm_mailbox_0; + uint32_t pmcu2spm_mailbox_1; + uint32_t pmcu2spm_mailbox_2; + uint32_t pmcu2spm_mailbox_3; + uint32_t ufs_psri_sw; + uint32_t ufs_psri_sw_set; + uint32_t ufs_psri_sw_clr; + uint32_t spm_ap_sema; + uint32_t spm_spm_sema; + uint32_t spm_dvfs_con; + uint32_t spm_dvfs_con_sta; + uint32_t spm_pmic_spmi_con; + uint8_t reserved19[4]; + uint32_t spm_dvfs_cmd0; + uint32_t spm_dvfs_cmd1; + uint32_t spm_dvfs_cmd2; + uint32_t spm_dvfs_cmd3; + uint32_t spm_dvfs_cmd4; + uint32_t spm_dvfs_cmd5; + uint32_t spm_dvfs_cmd6; + uint32_t spm_dvfs_cmd7; + uint32_t spm_dvfs_cmd8; + uint32_t spm_dvfs_cmd9; + uint32_t spm_dvfs_cmd10; + uint32_t spm_dvfs_cmd11; + uint32_t spm_dvfs_cmd12; + uint32_t spm_dvfs_cmd13; + uint32_t spm_dvfs_cmd14; + uint32_t spm_dvfs_cmd15; + uint32_t spm_dvfs_cmd16; + uint32_t spm_dvfs_cmd17; + uint32_t spm_dvfs_cmd18; + uint32_t spm_dvfs_cmd19; + uint32_t spm_dvfs_cmd20; + uint32_t spm_dvfs_cmd21; + uint32_t spm_dvfs_cmd22; + uint32_t spm_dvfs_cmd23; + uint32_t sys_timer_value_l; + uint32_t sys_timer_value_h; + uint32_t sys_timer_start_l; + uint32_t sys_timer_start_h; + uint32_t sys_timer_latch_l_00; + uint32_t sys_timer_latch_h_00; + uint32_t sys_timer_latch_l_01; + uint32_t sys_timer_latch_h_01; + uint32_t sys_timer_latch_l_02; + uint32_t sys_timer_latch_h_02; + uint32_t sys_timer_latch_l_03; + uint32_t sys_timer_latch_h_03; + uint32_t sys_timer_latch_l_04; + uint32_t sys_timer_latch_h_04; + uint32_t sys_timer_latch_l_05; + uint32_t sys_timer_latch_h_05; + uint32_t sys_timer_latch_l_06; + uint32_t sys_timer_latch_h_06; + uint32_t sys_timer_latch_l_07; + uint32_t sys_timer_latch_h_07; + uint32_t sys_timer_latch_l_08; + uint32_t sys_timer_latch_h_08; + uint32_t sys_timer_latch_l_09; + uint32_t sys_timer_latch_h_09; + uint32_t sys_timer_latch_l_10; + uint32_t sys_timer_latch_h_10; + uint32_t sys_timer_latch_l_11; + uint32_t sys_timer_latch_h_11; + uint32_t sys_timer_latch_l_12; + uint32_t sys_timer_latch_h_12; + uint32_t sys_timer_latch_l_13; + uint32_t sys_timer_latch_h_13; + uint32_t sys_timer_latch_l_14; + uint32_t sys_timer_latch_h_14; + uint32_t sys_timer_latch_l_15; + uint32_t sys_timer_latch_h_15; + uint32_t pcm_wdt_latch_0; + uint32_t pcm_wdt_latch_1; + uint32_t pcm_wdt_latch_2; + uint32_t pcm_wdt_latch_3; + uint32_t pcm_wdt_latch_4; + uint32_t pcm_wdt_latch_5; + uint32_t pcm_wdt_latch_6; + uint32_t pcm_wdt_latch_7; + uint32_t pcm_wdt_latch_8; + uint32_t pcm_wdt_latch_9; + uint32_t pcm_wdt_latch_10; + uint32_t pcm_wdt_latch_11; + uint32_t pcm_wdt_latch_12; + uint32_t pcm_wdt_latch_13; + uint32_t pcm_wdt_latch_14; + uint32_t pcm_wdt_latch_15; + uint32_t pcm_wdt_latch_16; + uint32_t pcm_wdt_latch_17; + uint32_t pcm_wdt_latch_18; + uint32_t pcm_wdt_latch_spare_0; + uint32_t pcm_wdt_latch_spare_1; + uint32_t pcm_wdt_latch_spare_2; + uint8_t reserved20[24]; + uint32_t pcm_wdt_latch_conn_0; + uint32_t pcm_wdt_latch_conn_1; + uint32_t pcm_wdt_latch_conn_2; + uint8_t reserved21[36]; + uint32_t dramc_gating_err_latch_ch0_0; + uint32_t dramc_gating_err_latch_ch0_1; + uint32_t dramc_gating_err_latch_ch0_2; + uint32_t dramc_gating_err_latch_ch0_3; + uint32_t dramc_gating_err_latch_ch0_4; + uint32_t dramc_gating_err_latch_ch0_5; + uint32_t dramc_gating_err_latch_ch0_6; + uint8_t reserved22[56]; + uint32_t dramc_gating_err_latch_spare_0; + uint8_t reserved23[8]; + uint32_t spm_ack_chk_con_0; + uint32_t spm_ack_chk_pc_0; + uint32_t spm_ack_chk_sel_0; + uint32_t spm_ack_chk_timer_0; + uint32_t spm_ack_chk_sta_0; + uint32_t spm_ack_chk_swint_0; + uint32_t spm_ack_chk_con_1; + uint32_t spm_ack_chk_pc_1; + uint32_t spm_ack_chk_sel_1; + uint32_t spm_ack_chk_timer_1; + uint32_t spm_ack_chk_sta_1; + uint32_t spm_ack_chk_swint_1; + uint32_t spm_ack_chk_con_2; + uint32_t spm_ack_chk_pc_2; + uint32_t spm_ack_chk_sel_2; + uint32_t spm_ack_chk_timer_2; + uint32_t spm_ack_chk_sta_2; + uint32_t spm_ack_chk_swint_2; + uint32_t spm_ack_chk_con_3; + uint32_t spm_ack_chk_pc_3; + uint32_t spm_ack_chk_sel_3; + uint32_t spm_ack_chk_timer_3; + uint32_t spm_ack_chk_sta_3; + uint32_t spm_ack_chk_swint_3; + uint32_t spm_counter_0; + uint32_t spm_counter_1; + uint32_t spm_counter_2; + uint32_t sys_timer_con; + uint32_t spm_twam_con; + uint32_t spm_twam_window_len; + uint32_t spm_twam_idle_sel; + uint32_t spm_twam_event_clear; + uint32_t opp0_table; + uint32_t opp1_table; + uint32_t opp2_table; + uint32_t opp3_table; + uint32_t opp4_table; + uint32_t opp5_table; + uint32_t opp6_table; + uint32_t opp7_table; + uint32_t opp8_table; + uint32_t opp9_table; + uint32_t opp10_table; + uint32_t opp11_table; + uint32_t opp12_table; + uint32_t opp13_table; + uint32_t opp14_table; + uint32_t opp15_table; + uint32_t opp16_table; + uint32_t opp17_table; + uint32_t shu0_array; + uint32_t shu1_array; + uint32_t shu2_array; + uint32_t shu3_array; + uint32_t shu4_array; + uint32_t shu5_array; + uint32_t shu6_array; + uint32_t shu7_array; + uint32_t shu8_array; + uint32_t shu9_array; + uint32_t ssusb_top_pwr_con; + uint32_t ssusb_top_p1_pwr_con; + uint32_t adsp_infra_pwr_con; + uint32_t adsp_ao_pwr_con; +}; + +check_member(mtk_spm_regs, ap_mdsrc_req, 0x430); +check_member(mtk_spm_regs, ssusb_top_pwr_con, 0x9F0); +check_member(mtk_spm_regs, ssusb_top_p1_pwr_con, 0x9F4); +check_member(mtk_spm_regs, adsp_infra_pwr_con, 0x9F8); +check_member(mtk_spm_regs, adsp_ao_pwr_con, 0x9FC); + +static struct mtk_spm_regs *const mtk_spm = (void *)SPM_BASE; + +#endif /* SOC_MEDIATEK_MT8186_SPM_H */ |