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-rw-r--r--src/southbridge/intel/fsp_bd82x6x/early_smbus.c2
-rw-r--r--src/southbridge/intel/fsp_bd82x6x/early_usb.c4
-rw-r--r--src/southbridge/intel/fsp_bd82x6x/smihandler.c2
3 files changed, 4 insertions, 4 deletions
diff --git a/src/southbridge/intel/fsp_bd82x6x/early_smbus.c b/src/southbridge/intel/fsp_bd82x6x/early_smbus.c
index 755795fa4c..10b4287d0f 100644
--- a/src/southbridge/intel/fsp_bd82x6x/early_smbus.c
+++ b/src/southbridge/intel/fsp_bd82x6x/early_smbus.c
@@ -69,7 +69,7 @@ static int smbus_wait_until_done(u16 smbus_base)
*/
void enable_smbus(void)
{
- device_t dev;
+ pci_devfn_t dev;
/* Set the SMBus device statically. */
dev = PCI_DEV(0x0, 0x1f, 0x3);
diff --git a/src/southbridge/intel/fsp_bd82x6x/early_usb.c b/src/southbridge/intel/fsp_bd82x6x/early_usb.c
index 8fac3c7745..4b9061e800 100644
--- a/src/southbridge/intel/fsp_bd82x6x/early_usb.c
+++ b/src/southbridge/intel/fsp_bd82x6x/early_usb.c
@@ -32,8 +32,8 @@
*/
void enable_usb_bar(void)
{
- device_t usb0 = PCH_EHCI1_DEV;
- device_t usb1 = PCH_EHCI2_DEV;
+ pci_devfn_t usb0 = PCH_EHCI1_DEV;
+ pci_devfn_t usb1 = PCH_EHCI2_DEV;
u32 cmd;
/* USB Controller 1 */
diff --git a/src/southbridge/intel/fsp_bd82x6x/smihandler.c b/src/southbridge/intel/fsp_bd82x6x/smihandler.c
index 83eab79b87..90ed943cba 100644
--- a/src/southbridge/intel/fsp_bd82x6x/smihandler.c
+++ b/src/southbridge/intel/fsp_bd82x6x/smihandler.c
@@ -242,7 +242,7 @@ static void busmaster_disable_on_bus(int bus)
for (slot = 0; slot < 0x20; slot++) {
for (func = 0; func < 8; func++) {
u32 reg32;
- device_t dev = PCI_DEV(bus, slot, func);
+ pci_devfn_t dev = PCI_DEV(bus, slot, func);
val = pci_read_config32(dev, PCI_VENDOR_ID);