diff options
| -rw-r--r-- | src/mainboard/google/brya/dsdt.asl | 2 | ||||
| -rw-r--r-- | src/mainboard/google/brya/mainboard.asl | 24 | ||||
| -rw-r--r-- | src/mainboard/google/brya/variants/baseboard/include/baseboard/gpio.h | 10 |
3 files changed, 32 insertions, 4 deletions
diff --git a/src/mainboard/google/brya/dsdt.asl b/src/mainboard/google/brya/dsdt.asl index 7bcba7f9d7..2bfb49713e 100644 --- a/src/mainboard/google/brya/dsdt.asl +++ b/src/mainboard/google/brya/dsdt.asl @@ -22,6 +22,8 @@ DefinitionBlock( #include <cpu/intel/common/acpi/cpu.asl> Scope (\_SB) { + #include "mainboard.asl" + Device (PCI0) { #include <soc/intel/common/block/acpi/acpi/northbridge.asl> diff --git a/src/mainboard/google/brya/mainboard.asl b/src/mainboard/google/brya/mainboard.asl new file mode 100644 index 0000000000..c60db3081c --- /dev/null +++ b/src/mainboard/google/brya/mainboard.asl @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/gpio.h> + +/* + * S0ix Entry/Exit Notifications + * Called from \_SB.PEPD._DSM + */ +Method (MS0X, 1, Serialized) +{ + If (Arg0 == 1) { + /* + * On S0ix entry, clear the SLP_S0_GATE pin, so that the rest of + * the platform can transition to its low power state as well. + */ + \_SB.PCI0.CTXS(GPIO_SLP_S0_GATE); + } Else { + /* + * On S0ix exit, set the SLP_S0_GATE pin, so that the rest of + * the platform will resume from its low power state. + */ + \_SB.PCI0.STXS(GPIO_SLP_S0_GATE); + } +} diff --git a/src/mainboard/google/brya/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/brya/variants/baseboard/include/baseboard/gpio.h index 96e88b56d1..578fac9de9 100644 --- a/src/mainboard/google/brya/variants/baseboard/include/baseboard/gpio.h +++ b/src/mainboard/google/brya/variants/baseboard/include/baseboard/gpio.h @@ -7,12 +7,14 @@ #include <soc/gpio.h> /* eSPI virtual wire reporting */ -#define EC_SCI_GPI GPE0_ESPI +#define EC_SCI_GPI GPE0_ESPI /* EC wake is EC_PCH_INT which is routed to GPP_F17 pin */ -#define GPE_EC_WAKE GPE0_DW2_17 +#define GPE_EC_WAKE GPE0_DW2_17 /* WP signal to PCH */ -#define GPIO_PCH_WP GPP_E15 +#define GPIO_PCH_WP GPP_E15 /* EC in RW or RO */ -#define GPIO_EC_IN_RW GPP_F18 +#define GPIO_EC_IN_RW GPP_F18 +/* Used to gate SoC's SLP_S0# signal */ +#define GPIO_SLP_S0_GATE GPP_F9 #endif /* __BASEBOARD_GPIO_H__ */ |