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-rw-r--r--src/soc/intel/cannonlake/lpc.c18
1 files changed, 18 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/lpc.c b/src/soc/intel/cannonlake/lpc.c
index 60729f144a..c02d66e54d 100644
--- a/src/soc/intel/cannonlake/lpc.c
+++ b/src/soc/intel/cannonlake/lpc.c
@@ -203,4 +203,22 @@ void lpc_soc_init(struct device *dev)
i8259_configure_irq_trigger(9, 1);
clock_gate_8254(dev);
}
+
+/* Fill up LPC IO resource structure inside SoC directory */
+void pch_lpc_soc_fill_io_resources(struct device *dev)
+{
+ /*
+ * PMC pci device gets hidden from PCI bus due to Silicon
+ * policy hence bind ACPI BASE aka ABASE (offset 0x20) with
+ * LPC IO resources to ensure that ABASE falls under PCI reserved
+ * IO memory range.
+ *
+ * Note: Don't add any more resource with same offset 0x20
+ * under this device space.
+ */
+ pch_lpc_add_new_resource(dev, PCI_BASE_ADDRESS_4,
+ ACPI_BASE_ADDRESS, ACPI_BASE_SIZE, IORESOURCE_IO |
+ IORESOURCE_ASSIGNED | IORESOURCE_FIXED);
+}
+
#endif