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-rw-r--r--src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspmUpd.h724
-rw-r--r--src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspsUpd.h320
2 files changed, 518 insertions, 526 deletions
diff --git a/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspmUpd.h
index c40f11de58..f4892793d4 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspmUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspmUpd.h
@@ -771,11 +771,9 @@ typedef struct {
**/
UINT8 RealtimeMemoryTiming;
-/** Offset 0x0232 - This is policy to control iTBT PCIe Multiple Segment setting.
- DEPRECATED
- $EN_DIS
+/** Offset 0x0232 - Reserved
**/
- UINT8 PcieMultipleSegmentEnabled;
+ UINT8 Reserved13;
/** Offset 0x0233 - Enable/Disable SA IPU
Enable(Default): Enable SA IPU, Disable: Disable SA IPU
@@ -887,7 +885,7 @@ typedef struct {
/** Offset 0x024A - Reserved
**/
- UINT8 Reserved13[14];
+ UINT8 Reserved14[14];
/** Offset 0x0258 - Per-core HT Disable
Defines the per-core HT disable mask where: 1 - Disable selected logical core HT,
@@ -899,10 +897,10 @@ typedef struct {
/** Offset 0x025A - Reserved
**/
- UINT8 Reserved14[6];
+ UINT8 Reserved15[6];
/** Offset 0x0260 - Thermal Velocity Boost Ratio clipping
- 0(Default): Disabled, 1: Enabled. This service controls Core frequency reduction
+ 0: Disabled, 1(Default): Enabled. This service controls Core frequency reduction
caused by high package temperatures for processors that implement the Intel Thermal
Velocity Boost (TVB) feature
$EN_DIS
@@ -918,7 +916,7 @@ typedef struct {
/** Offset 0x0262 - Reserved
**/
- UINT8 Reserved15[47];
+ UINT8 Reserved16[47];
/** Offset 0x0291 - DMI Max Link Speed
Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1
@@ -1023,7 +1021,7 @@ typedef struct {
/** Offset 0x02C3 - Reserved
**/
- UINT8 Reserved16[16];
+ UINT8 Reserved17[16];
/** Offset 0x02D3 - Enable/Disable DMI GEN3 DmiGen3DsPresetEnable
Enable/Disable DMI GEN3 DmiGen3DsPreset. Auto(0x0)(Default): DmiGen3DsPresetEnable,
@@ -1065,7 +1063,7 @@ typedef struct {
/** Offset 0x02F5 - Reserved
**/
- UINT8 Reserved17[54];
+ UINT8 Reserved18[54];
/** Offset 0x032B - DMI ASPM L1 exit Latency
Range: 0-7, 4 is default L1 exit Latency
@@ -1074,7 +1072,7 @@ typedef struct {
/** Offset 0x032C - Reserved
**/
- UINT8 Reserved18[40];
+ UINT8 Reserved19[40];
/** Offset 0x0354 - BIST on Reset
Enable/Disable BIST (Built-In Self Test) on reset. <b>0: Disable</b>; 1: Enable.
@@ -1139,7 +1137,7 @@ typedef struct {
/** Offset 0x035E - Reserved
**/
- UINT8 Reserved19;
+ UINT8 Reserved20;
/** Offset 0x035F - Number of active big cores
Number of P-cores to enable in each processor package. Note: Number of P-Cores and
@@ -1183,7 +1181,7 @@ typedef struct {
/** Offset 0x0365 - Reserved
**/
- UINT8 Reserved20;
+ UINT8 Reserved21;
/** Offset 0x0366 - core voltage override
The core voltage override which is applied to the entire range of cpu core frequencies.
@@ -1271,7 +1269,7 @@ typedef struct {
/** Offset 0x037A - Reserved
**/
- UINT8 Reserved21[67];
+ UINT8 Reserved22[67];
/** Offset 0x03BD - Core VF Point Offset Mode
Selects Core Voltage & Frequency Offset mode between Legacy and Selection modes.
@@ -1306,7 +1304,7 @@ typedef struct {
/** Offset 0x03FB - Reserved
**/
- UINT8 Reserved22[25];
+ UINT8 Reserved23[25];
/** Offset 0x0414 - Per Core Max Ratio override
Enable or disable Per Core PState OC supported by writing OCMB 0x1D to program new
@@ -1317,7 +1315,7 @@ typedef struct {
/** Offset 0x0415 - Reserved
**/
- UINT8 Reserved23[41];
+ UINT8 Reserved24[41];
/** Offset 0x043E - Per Core Current Max Ratio
Array for the Per Core Max Ratio
@@ -1326,9 +1324,9 @@ typedef struct {
/** Offset 0x0446 - Reserved
**/
- UINT8 Reserved24[13];
+ UINT8 Reserved25[69];
-/** Offset 0x0453 - Pvd Ratio Threshold for SOC/CPU die
+/** Offset 0x048B - Pvd Ratio Threshold for SOC/CPU die
Array of Pvd Ratio Threshold for SOC/CPU die is the threshold value for input ratio
(P0 to Pn) to select the multiplier so that the output is within the DCO frequency
range. As per the die selected, this threshold is applied to SA and MC/CMI PLL
@@ -1337,76 +1335,76 @@ typedef struct {
**/
UINT8 PvdRatioThreshold[2];
-/** Offset 0x0455 - Reserved
+/** Offset 0x048D - Reserved
**/
- UINT8 Reserved25[70];
+ UINT8 Reserved26[70];
-/** Offset 0x049B - BCLK Frequency Source
+/** Offset 0x04D3 - BCLK Frequency Source
Clock source of BCLK OC frequency, <b>0:CPU BCLK</b>, 1:PCH BCLK, 2:External CLK
0:CPU BCLK, 1:PCH BCLK, 2:External CLK
**/
UINT8 BclkSource;
-/** Offset 0x049C - GPIO Override
+/** Offset 0x04D4 - GPIO Override
Gpio Override Level - FSP will not configure any GPIOs and rely on GPIO setings
before moved to FSP. Available configurations 0: Disable; 1: Level 1 - Skips GPIO
configuration in PEI/FSPM/FSPT phase;2: Level 2 - Reserved for use
**/
UINT8 GpioOverride;
-/** Offset 0x049D - Reserved
+/** Offset 0x04D5 - Reserved
**/
- UINT8 Reserved26[3];
+ UINT8 Reserved27[7];
-/** Offset 0x04A0 - CPU BCLK OC Frequency
+/** Offset 0x04DC - CPU BCLK OC Frequency
CPU BCLK OC Frequency in KHz units. 98000000Hz = 98MHz <b>0 - Auto</b>. Range is
40Mhz-1000Mhz.
**/
UINT32 CpuBclkOcFrequency;
-/** Offset 0x04A4 - Reserved
+/** Offset 0x04E0 - Reserved
**/
- UINT8 Reserved27[4];
+ UINT8 Reserved28[4];
-/** Offset 0x04A8 - Enable CPU CrashLog GPRs dump
+/** Offset 0x04E4 - Enable CPU CrashLog GPRs dump
Enable or Disable CPU CrashLog GPRs dump; <b>0: Disable</b>; 1: Enable; 2: Only
disable Smm GPRs dump
0:Disabled, 1:Enabled, 2:Only Smm GPRs Disabled
**/
UINT8 CrashLogGprs;
-/** Offset 0x04A9 - Reserved
+/** Offset 0x04E5 - Reserved
**/
- UINT8 Reserved28[253];
+ UINT8 Reserved29[269];
-/** Offset 0x05A6 - Thermal Design Current enable/disable
+/** Offset 0x05F2 - Thermal Design Current enable/disable
Thermal Design Current enable/disable; <b>0: Disable</b>; 1: Enable. [0] for IA,
[1] for GT, [2] for SA, [3] through [5] are Reserved.
**/
UINT8 TdcEnable[6];
-/** Offset 0x05AC - Thermal Design Current time window
+/** Offset 0x05F8 - Thermal Design Current time window
TDC Time Window, value of IA either in milliseconds or seconds, value of GT/SA is
in milliseconds. 1ms is default. Range of IA from 1ms to 448s, Range of GT/SA is
1ms to 10ms, except for 9ms. 9ms has no valid encoding in the MSR definition.
**/
UINT32 TdcTimeWindow[6];
-/** Offset 0x05C4 - Reserved
+/** Offset 0x0610 - Reserved
**/
- UINT8 Reserved29[204];
+ UINT8 Reserved30[208];
-/** Offset 0x0690 - BiosGuard
+/** Offset 0x06E0 - BiosGuard
Enable/Disable. 0: Disable, Enable/Disable BIOS Guard feature, 1: enable
$EN_DIS
**/
UINT8 BiosGuard;
-/** Offset 0x0691
+/** Offset 0x06E1
**/
UINT8 BiosGuardToolsInterface;
-/** Offset 0x0692 - Txt
+/** Offset 0x06E2 - Txt
Enables utilization of additional hardware capabilities provided by Intel (R) Trusted
Execution Technology. Changes require a full power cycle to take effect. <b>0:
Disable</b>, 1: Enable
@@ -1414,1254 +1412,1254 @@ typedef struct {
**/
UINT8 Txt;
-/** Offset 0x0693 - Reserved
+/** Offset 0x06E3 - Reserved
**/
- UINT8 Reserved30;
+ UINT8 Reserved31;
-/** Offset 0x0694 - PrmrrSize
+/** Offset 0x06E4 - PrmrrSize
Enable/Disable. 0: Disable, define default value of PrmrrSize , 1: enable
**/
UINT32 PrmrrSize;
-/** Offset 0x0698 - SinitMemorySize
+/** Offset 0x06E8 - SinitMemorySize
Enable/Disable. 0: Disable, define default value of SinitMemorySize , 1: enable
**/
UINT32 SinitMemorySize;
-/** Offset 0x069C - Reserved
+/** Offset 0x06EC - Reserved
**/
- UINT8 Reserved31[4];
+ UINT8 Reserved32[4];
-/** Offset 0x06A0 - TxtDprMemoryBase
+/** Offset 0x06F0 - TxtDprMemoryBase
Enable/Disable. 0: Disable, define default value of TxtDprMemoryBase , 1: enable
**/
UINT64 TxtDprMemoryBase;
-/** Offset 0x06A8 - TxtHeapMemorySize
+/** Offset 0x06F8 - TxtHeapMemorySize
Enable/Disable. 0: Disable, define default value of TxtHeapMemorySize , 1: enable
**/
UINT32 TxtHeapMemorySize;
-/** Offset 0x06AC - TxtDprMemorySize
+/** Offset 0x06FC - TxtDprMemorySize
Reserve DPR memory size (0-255) MB. 0: Disable, define default value of TxtDprMemorySize
, 1: enable
**/
UINT32 TxtDprMemorySize;
-/** Offset 0x06B0 - BiosAcmBase
+/** Offset 0x0700 - BiosAcmBase
Enable/Disable. 0: Disable, define default value of BiosAcmBase , 1: enable
**/
UINT32 BiosAcmBase;
-/** Offset 0x06B4 - BiosAcmSize
+/** Offset 0x0704 - BiosAcmSize
Enable/Disable. 0: Disable, define default value of BiosAcmSize , 1: enable
**/
UINT32 BiosAcmSize;
-/** Offset 0x06B8 - ApStartupBase
+/** Offset 0x0708 - ApStartupBase
Enable/Disable. 0: Disable, define default value of BiosAcmBase , 1: enable
**/
UINT32 ApStartupBase;
-/** Offset 0x06BC - TgaSize
+/** Offset 0x070C - TgaSize
Enable/Disable. 0: Disable, define default value of TgaSize , 1: enable
**/
UINT32 TgaSize;
-/** Offset 0x06C0 - TxtLcpPdBase
+/** Offset 0x0710 - TxtLcpPdBase
Enable/Disable. 0: Disable, define default value of TxtLcpPdBase , 1: enable
**/
UINT64 TxtLcpPdBase;
-/** Offset 0x06C8 - TxtLcpPdSize
+/** Offset 0x0718 - TxtLcpPdSize
Enable/Disable. 0: Disable, define default value of TxtLcpPdSize , 1: enable
**/
UINT64 TxtLcpPdSize;
-/** Offset 0x06D0 - IsTPMPresence
+/** Offset 0x0720 - IsTPMPresence
IsTPMPresence default values
**/
UINT8 IsTPMPresence;
-/** Offset 0x06D1 - Reserved
+/** Offset 0x0721 - Reserved
**/
- UINT8 Reserved32[32];
+ UINT8 Reserved33[32];
-/** Offset 0x06F1 - Enable PCH HSIO PCIE Rx Set Ctle
+/** Offset 0x0741 - Enable PCH HSIO PCIE Rx Set Ctle
Enable PCH PCIe Gen 3 Set CTLE Value.
**/
UINT8 PchPcieHsioRxSetCtleEnable[28];
-/** Offset 0x070D - PCH HSIO PCIE Rx Set Ctle Value
+/** Offset 0x075D - PCH HSIO PCIE Rx Set Ctle Value
PCH PCIe Gen 3 Set CTLE Value.
**/
UINT8 PchPcieHsioRxSetCtle[28];
-/** Offset 0x0729 - Enble PCH HSIO PCIE TX Gen 1 Downscale Amplitude Adjustment value override
+/** Offset 0x0779 - Enble PCH HSIO PCIE TX Gen 1 Downscale Amplitude Adjustment value override
0: Disable; 1: Enable.
**/
UINT8 PchPcieHsioTxGen1DownscaleAmpEnable[28];
-/** Offset 0x0745 - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value
+/** Offset 0x0795 - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value
PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value.
**/
UINT8 PchPcieHsioTxGen1DownscaleAmp[28];
-/** Offset 0x0761 - Enable PCH HSIO PCIE TX Gen 2 Downscale Amplitude Adjustment value override
+/** Offset 0x07B1 - Enable PCH HSIO PCIE TX Gen 2 Downscale Amplitude Adjustment value override
0: Disable; 1: Enable.
**/
UINT8 PchPcieHsioTxGen2DownscaleAmpEnable[28];
-/** Offset 0x077D - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value
+/** Offset 0x07CD - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value
PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value.
**/
UINT8 PchPcieHsioTxGen2DownscaleAmp[28];
-/** Offset 0x0799 - Enable PCH HSIO PCIE TX Gen 3 Downscale Amplitude Adjustment value override
+/** Offset 0x07E9 - Enable PCH HSIO PCIE TX Gen 3 Downscale Amplitude Adjustment value override
0: Disable; 1: Enable.
**/
UINT8 PchPcieHsioTxGen3DownscaleAmpEnable[28];
-/** Offset 0x07B5 - PCH HSIO PCIE Gen 3 TX Output Downscale Amplitude Adjustment value
+/** Offset 0x0805 - PCH HSIO PCIE Gen 3 TX Output Downscale Amplitude Adjustment value
PCH PCIe Gen 3 TX Output Downscale Amplitude Adjustment value.
**/
UINT8 PchPcieHsioTxGen3DownscaleAmp[28];
-/** Offset 0x07D1 - Enable PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment Setting value override
+/** Offset 0x0821 - Enable PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment Setting value override
0: Disable; 1: Enable.
**/
UINT8 PchPcieHsioTxGen1DeEmphEnable[28];
-/** Offset 0x07ED - PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment value
+/** Offset 0x083D - PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment value
PCH PCIe Gen 1 TX Output De-Emphasis Adjustment Setting.
**/
UINT8 PchPcieHsioTxGen1DeEmph[28];
-/** Offset 0x0809 - Enable PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting value override
+/** Offset 0x0859 - Enable PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting value override
0: Disable; 1: Enable.
**/
UINT8 PchPcieHsioTxGen2DeEmph3p5Enable[28];
-/** Offset 0x0825 - PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment value
+/** Offset 0x0875 - PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment value
PCH PCIe Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting.
**/
UINT8 PchPcieHsioTxGen2DeEmph3p5[28];
-/** Offset 0x0841 - Enable PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting value override
+/** Offset 0x0891 - Enable PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting value override
0: Disable; 1: Enable.
**/
UINT8 PchPcieHsioTxGen2DeEmph6p0Enable[28];
-/** Offset 0x085D - PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment value
+/** Offset 0x08AD - PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment value
PCH PCIe Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting.
**/
UINT8 PchPcieHsioTxGen2DeEmph6p0[28];
-/** Offset 0x0879 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override
+/** Offset 0x08C9 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override
0: Disable; 1: Enable.
**/
UINT8 PchSataHsioRxGen1EqBoostMagEnable[8];
-/** Offset 0x0881 - PCH HSIO SATA 1.5 Gb/s Receiver Equalization Boost Magnitude Adjustment value
+/** Offset 0x08D1 - PCH HSIO SATA 1.5 Gb/s Receiver Equalization Boost Magnitude Adjustment value
PCH HSIO SATA 1.5 Gb/s Receiver Equalization Boost Magnitude Adjustment value.
**/
UINT8 PchSataHsioRxGen1EqBoostMag[8];
-/** Offset 0x0889 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override
+/** Offset 0x08D9 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override
0: Disable; 1: Enable.
**/
UINT8 PchSataHsioRxGen2EqBoostMagEnable[8];
-/** Offset 0x0891 - PCH HSIO SATA 3.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value
+/** Offset 0x08E1 - PCH HSIO SATA 3.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value
PCH HSIO SATA 3.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value.
**/
UINT8 PchSataHsioRxGen2EqBoostMag[8];
-/** Offset 0x0899 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override
+/** Offset 0x08E9 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override
0: Disable; 1: Enable.
**/
UINT8 PchSataHsioRxGen3EqBoostMagEnable[8];
-/** Offset 0x08A1 - PCH HSIO SATA 6.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value
+/** Offset 0x08F1 - PCH HSIO SATA 6.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value
PCH HSIO SATA 6.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value.
**/
UINT8 PchSataHsioRxGen3EqBoostMag[8];
-/** Offset 0x08A9 - Enable PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value override
+/** Offset 0x08F9 - Enable PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value override
0: Disable; 1: Enable.
**/
UINT8 PchSataHsioTxGen1DownscaleAmpEnable[8];
-/** Offset 0x08B1 - PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value
+/** Offset 0x0901 - PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value
PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value.
**/
UINT8 PchSataHsioTxGen1DownscaleAmp[8];
-/** Offset 0x08B9 - Enable PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value override
+/** Offset 0x0909 - Enable PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value override
0: Disable; 1: Enable.
**/
UINT8 PchSataHsioTxGen2DownscaleAmpEnable[8];
-/** Offset 0x08C1 - PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value
+/** Offset 0x0911 - PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value
PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value.
**/
UINT8 PchSataHsioTxGen2DownscaleAmp[8];
-/** Offset 0x08C9 - Enable PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value override
+/** Offset 0x0919 - Enable PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value override
0: Disable; 1: Enable.
**/
UINT8 PchSataHsioTxGen3DownscaleAmpEnable[8];
-/** Offset 0x08D1 - PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value
+/** Offset 0x0921 - PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value
PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value.
**/
UINT8 PchSataHsioTxGen3DownscaleAmp[8];
-/** Offset 0x08D9 - Enable PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting value override
+/** Offset 0x0929 - Enable PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting value override
0: Disable; 1: Enable.
**/
UINT8 PchSataHsioTxGen1DeEmphEnable[8];
-/** Offset 0x08E1 - PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting
+/** Offset 0x0931 - PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting
PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting.
**/
UINT8 PchSataHsioTxGen1DeEmph[8];
-/** Offset 0x08E9 - Enable PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting value override
+/** Offset 0x0939 - Enable PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting value override
0: Disable; 1: Enable.
**/
UINT8 PchSataHsioTxGen2DeEmphEnable[8];
-/** Offset 0x08F1 - PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting
+/** Offset 0x0941 - PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting
PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting.
**/
UINT8 PchSataHsioTxGen2DeEmph[8];
-/** Offset 0x08F9 - Enable PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting value override
+/** Offset 0x0949 - Enable PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting value override
0: Disable; 1: Enable.
**/
UINT8 PchSataHsioTxGen3DeEmphEnable[8];
-/** Offset 0x0901 - PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting
+/** Offset 0x0951 - PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting
PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting.
**/
UINT8 PchSataHsioTxGen3DeEmph[8];
-/** Offset 0x0909 - PCH LPC Enhance the port 8xh decoding
+/** Offset 0x0959 - PCH LPC Enhance the port 8xh decoding
Original LPC only decodes one byte of port 80h.
$EN_DIS
**/
UINT8 PchLpcEnhancePort8xhDecoding;
-/** Offset 0x090A - PCH Port80 Route
+/** Offset 0x095A - PCH Port80 Route
Control where the Port 80h cycles are sent, 0: LPC; 1: PCI.
$EN_DIS
**/
UINT8 PchPort80Route;
-/** Offset 0x090B - Enable SMBus ARP support
+/** Offset 0x095B - Enable SMBus ARP support
Enable SMBus ARP support.
$EN_DIS
**/
UINT8 SmbusArpEnable;
-/** Offset 0x090C - Number of RsvdSmbusAddressTable.
+/** Offset 0x095C - Number of RsvdSmbusAddressTable.
The number of elements in the RsvdSmbusAddressTable.
**/
UINT8 PchNumRsvdSmbusAddresses;
-/** Offset 0x090D - Reserved
+/** Offset 0x095D - Reserved
**/
- UINT8 Reserved33;
+ UINT8 Reserved34;
-/** Offset 0x090E - SMBUS Base Address
+/** Offset 0x095E - SMBUS Base Address
SMBUS Base Address (IO space).
**/
UINT16 PchSmbusIoBase;
-/** Offset 0x0910 - Enable SMBus Alert Pin
+/** Offset 0x0960 - Enable SMBus Alert Pin
Enable SMBus Alert Pin.
$EN_DIS
**/
UINT8 PchSmbAlertEnable;
-/** Offset 0x0911 - Usage type for ClkSrc
+/** Offset 0x0961 - Usage type for ClkSrc
0-23: PCH rootport, 0x70:LAN, 0x80: unspecified but in use (free running), 0xFF: not used
**/
UINT8 PcieClkSrcUsage[18];
-/** Offset 0x0923 - Reserved
+/** Offset 0x0973 - Reserved
**/
- UINT8 Reserved34[14];
+ UINT8 Reserved35[14];
-/** Offset 0x0931 - ClkReq-to-ClkSrc mapping
+/** Offset 0x0981 - ClkReq-to-ClkSrc mapping
Number of ClkReq signal assigned to ClkSrc
**/
UINT8 PcieClkSrcClkReq[18];
-/** Offset 0x0943 - Reserved
+/** Offset 0x0993 - Reserved
**/
- UINT8 Reserved35[57];
+ UINT8 Reserved36[57];
-/** Offset 0x097C - Enable SOC/IOE PCIE RP Mask
+/** Offset 0x09CC - Enable SOC/IOE PCIE RP Mask
Enable/disable SOC/IOE PCIE Root Ports. 0: disable, 1: enable. One bit for each
port, bit0 for port1, bit1 for port2, and so on.
**/
UINT16 PcieRpEnableMask;
-/** Offset 0x097E - VC Type
+/** Offset 0x09CE - VC Type
Virtual Channel Type Select: 0: VC0, 1: VC1.
0: VC0, 1: VC1
**/
UINT8 PchHdaVcType;
-/** Offset 0x097F - Universal Audio Architecture compliance for DSP enabled system
+/** Offset 0x09CF - Universal Audio Architecture compliance for DSP enabled system
0: Not-UAA Compliant (Intel SST driver supported only), 1: UAA Compliant (HDA Inbox
driver or SST driver supported).
$EN_DIS
**/
UINT8 PchHdaDspUaaCompliance;
-/** Offset 0x0980 - Enable HD Audio Link
+/** Offset 0x09D0 - Enable HD Audio Link
Enable/disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1.
$EN_DIS
**/
UINT8 PchHdaAudioLinkHdaEnable;
-/** Offset 0x0981 - Enable HDA SDI lanes
+/** Offset 0x09D1 - Enable HDA SDI lanes
Enable/disable HDA SDI lanes.
**/
UINT8 PchHdaSdiEnable[2];
-/** Offset 0x0983 - HDA Power/Clock Gating (PGD/CGD)
+/** Offset 0x09D3 - HDA Power/Clock Gating (PGD/CGD)
Enable/Disable HD Audio Power and Clock Gating(POR: Enable). 0: PLATFORM_POR, 1:
FORCE_ENABLE, 2: FORCE_DISABLE.
0: POR, 1: Force Enable, 2: Force Disable
**/
UINT8 PchHdaTestPowerClockGating;
-/** Offset 0x0984 - Enable HD Audio DMIC_N Link
+/** Offset 0x09D4 - Enable HD Audio DMIC_N Link
Enable/disable HD Audio DMIC1 link. Muxed with SNDW3.
**/
UINT8 PchHdaAudioLinkDmicEnable[2];
-/** Offset 0x0986 - Reserved
+/** Offset 0x09D6 - Reserved
**/
- UINT8 Reserved36[2];
+ UINT8 Reserved37[2];
-/** Offset 0x0988 - DMIC<N> ClkA Pin Muxing (N - DMIC number)
+/** Offset 0x09D8 - DMIC<N> ClkA Pin Muxing (N - DMIC number)
Determines DMIC<N> ClkA Pin muxing. See GPIO_*_MUXING_DMIC<N>_CLKA_*
**/
UINT32 PchHdaAudioLinkDmicClkAPinMux[2];
-/** Offset 0x0990 - DMIC<N> ClkB Pin Muxing
+/** Offset 0x09E0 - DMIC<N> ClkB Pin Muxing
Determines DMIC<N> ClkA Pin muxing. See GPIO_*_MUXING_DMIC<N>_CLKB_*
**/
UINT32 PchHdaAudioLinkDmicClkBPinMux[2];
-/** Offset 0x0998 - Enable HD Audio DSP
+/** Offset 0x09E8 - Enable HD Audio DSP
Enable/disable HD Audio DSP feature.
$EN_DIS
**/
UINT8 PchHdaDspEnable;
-/** Offset 0x0999 - Reserved
+/** Offset 0x09E9 - Reserved
**/
- UINT8 Reserved37[3];
+ UINT8 Reserved38[3];
-/** Offset 0x099C - DMIC<N> Data Pin Muxing
+/** Offset 0x09EC - DMIC<N> Data Pin Muxing
Determines DMIC<N> Data Pin muxing. See GPIO_*_MUXING_DMIC<N>_DATA_*
**/
UINT32 PchHdaAudioLinkDmicDataPinMux[2];
-/** Offset 0x09A4 - Enable HD Audio SSP0 Link
+/** Offset 0x09F4 - Enable HD Audio SSP0 Link
Enable/disable HD Audio SSP_N/I2S link. Muxed with HDA. N-number 0-5
**/
UINT8 PchHdaAudioLinkSspEnable[6];
-/** Offset 0x09AA - Enable HD Audio SoundWire#N Link
+/** Offset 0x09FA - Enable HD Audio SoundWire#N Link
Enable/disable HD Audio SNDW#N link. Muxed with HDA.
**/
UINT8 PchHdaAudioLinkSndwEnable[4];
-/** Offset 0x09AE - iDisp-Link Frequency
+/** Offset 0x09FE - iDisp-Link Frequency
iDisp-Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 4: 96MHz, 3: 48MHz.
4: 96MHz, 3: 48MHz
**/
UINT8 PchHdaIDispLinkFrequency;
-/** Offset 0x09AF - Reserved
+/** Offset 0x09FF - Reserved
**/
- UINT8 Reserved38;
+ UINT8 Reserved39;
-/** Offset 0x09B0 - iDisp-Link T-mode
+/** Offset 0x0A00 - iDisp-Link T-mode
iDisp-Link T-Mode (PCH_HDAUDIO_IDISP_TMODE enum): 0: 2T, 2: 4T, 3: 8T, 4: 16T
0: 2T, 2: 4T, 3: 8T, 4: 16T
**/
UINT8 PchHdaIDispLinkTmode;
-/** Offset 0x09B1 - iDisplay Audio Codec disconnection
+/** Offset 0x0A01 - iDisplay Audio Codec disconnection
0: Not disconnected, enumerable, 1: Disconnected SDI, not enumerable.
$EN_DIS
**/
UINT8 PchHdaIDispCodecDisconnect;
-/** Offset 0x09B2 - Reserved
+/** Offset 0x0A02 - Reserved
**/
- UINT8 Reserved39[6];
+ UINT8 Reserved40[6];
-/** Offset 0x09B8 - CNVi DDR RFI Mitigation
+/** Offset 0x0A08 - CNVi DDR RFI Mitigation
Enable/Disable DDR RFI Mitigation. Default is ENABLE. 0: DISABLE, 1: ENABLE
$EN_DIS
**/
UINT8 CnviDdrRfim;
-/** Offset 0x09B9 - Reserved
+/** Offset 0x0A09 - Reserved
**/
- UINT8 Reserved40[11];
+ UINT8 Reserved41[11];
-/** Offset 0x09C4 - Debug Interfaces
+/** Offset 0x0A14 - Debug Interfaces
Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub,
BIT2 - Not used.
**/
UINT8 PcdDebugInterfaceFlags;
-/** Offset 0x09C5 - Serial Io Uart Debug Controller Number
+/** Offset 0x0A15 - Serial Io Uart Debug Controller Number
Select SerialIo Uart Controller for debug.
0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2
**/
UINT8 SerialIoUartDebugControllerNumber;
-/** Offset 0x09C6 - Serial Io Uart Debug Auto Flow
+/** Offset 0x0A16 - Serial Io Uart Debug Auto Flow
Enables UART hardware flow control, CTS and RTS lines.
$EN_DIS
**/
UINT8 SerialIoUartDebugAutoFlow;
-/** Offset 0x09C7 - Reserved
+/** Offset 0x0A17 - Reserved
**/
- UINT8 Reserved41;
+ UINT8 Reserved42;
-/** Offset 0x09C8 - Serial Io Uart Debug BaudRate
+/** Offset 0x0A18 - Serial Io Uart Debug BaudRate
Set default BaudRate Supported from 0 - default to 6000000. Recommended values 9600,
19200, 57600, 115200, 460800, 921600, 1500000, 1843200, 3000000, 3686400, 6000000
**/
UINT32 SerialIoUartDebugBaudRate;
-/** Offset 0x09CC - Serial Io Uart Debug Parity
+/** Offset 0x0A1C - Serial Io Uart Debug Parity
Set default Parity.
0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity
**/
UINT8 SerialIoUartDebugParity;
-/** Offset 0x09CD - Serial Io Uart Debug Stop Bits
+/** Offset 0x0A1D - Serial Io Uart Debug Stop Bits
Set default stop bits.
0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3: TwoStopBits
**/
UINT8 SerialIoUartDebugStopBits;
-/** Offset 0x09CE - Serial Io Uart Debug Data Bits
+/** Offset 0x0A1E - Serial Io Uart Debug Data Bits
Set default word length. 0: Default, 5,6,7,8
5:5BITS, 6:6BITS, 7:7BITS, 8:8BITS
**/
UINT8 SerialIoUartDebugDataBits;
-/** Offset 0x09CF - Reserved
+/** Offset 0x0A1F - Reserved
**/
- UINT8 Reserved42;
+ UINT8 Reserved43;
-/** Offset 0x09D0 - Serial Io Uart Debug Mmio Base
+/** Offset 0x0A20 - Serial Io Uart Debug Mmio Base
Select SerialIo Uart default MMIO resource in SEC/PEI phase when PcdSerialIoUartMode
= SerialIoUartPci.
**/
UINT32 SerialIoUartDebugMmioBase;
-/** Offset 0x09D4 - ISA Serial Base selection
+/** Offset 0x0A24 - ISA Serial Base selection
Select ISA Serial Base address. Default is 0x3F8.
0:0x3F8, 1:0x2F8
**/
UINT8 PcdIsaSerialUartBase;
-/** Offset 0x09D5 - Reserved
+/** Offset 0x0A25 - Reserved
**/
- UINT8 Reserved43;
+ UINT8 Reserved44;
-/** Offset 0x09D6 - Ring PLL voltage offset
+/** Offset 0x0A26 - Ring PLL voltage offset
Core PLL voltage offset. <b>0: No offset</b>. Range 0-15
**/
UINT8 RingPllVoltageOffset;
-/** Offset 0x09D7 - System Agent PLL voltage offset
+/** Offset 0x0A27 - System Agent PLL voltage offset
Core PLL voltage offset. <b>0: No offset</b>. Range 0-15
**/
UINT8 SaPllVoltageOffset;
-/** Offset 0x09D8 - Reserved
+/** Offset 0x0A28 - Reserved
**/
- UINT8 Reserved44;
+ UINT8 Reserved45;
-/** Offset 0x09D9 - Memory Controller PLL voltage offset
+/** Offset 0x0A29 - Memory Controller PLL voltage offset
Core PLL voltage offset. <b>0: No offset</b>. Range 0-15
**/
UINT8 McPllVoltageOffset;
-/** Offset 0x09DA - TCSS Thunderbolt PCIE Root Port 0 Enable
+/** Offset 0x0A2A - TCSS Thunderbolt PCIE Root Port 0 Enable
Set TCSS Thunderbolt PCIE Root Port 0. 0:Disabled 1:Enabled
$EN_DIS
**/
UINT8 TcssItbtPcie0En;
-/** Offset 0x09DB - TCSS Thunderbolt PCIE Root Port 1 Enable
+/** Offset 0x0A2B - TCSS Thunderbolt PCIE Root Port 1 Enable
Set TCSS Thunderbolt PCIE Root Port 1. 0:Disabled 1:Enabled
$EN_DIS
**/
UINT8 TcssItbtPcie1En;
-/** Offset 0x09DC - TCSS Thunderbolt PCIE Root Port 2 Enable
+/** Offset 0x0A2C - TCSS Thunderbolt PCIE Root Port 2 Enable
Set TCSS Thunderbolt PCIE Root Port 2. 0:Disabled 1:Enabled
$EN_DIS
**/
UINT8 TcssItbtPcie2En;
-/** Offset 0x09DD - TCSS Thunderbolt PCIE Root Port 3 Enable
+/** Offset 0x0A2D - TCSS Thunderbolt PCIE Root Port 3 Enable
Set TCSS Thunderbolt PCIE Root Port 3. 0:Disabled 1:Enabled
$EN_DIS
**/
UINT8 TcssItbtPcie3En;
-/** Offset 0x09DE - TCSS USB HOST (xHCI) Enable
+/** Offset 0x0A2E - TCSS USB HOST (xHCI) Enable
Set TCSS XHCI. 0:Disabled 1:Enabled - Must be enabled if xDCI is enabled below
$EN_DIS
**/
UINT8 TcssXhciEn;
-/** Offset 0x09DF - TCSS USB DEVICE (xDCI) Enable
+/** Offset 0x0A2F - TCSS USB DEVICE (xDCI) Enable
Set TCSS XDCI. 0:Disabled 1:Enabled - xHCI must be enabled if xDCI is enabled
$EN_DIS
**/
UINT8 TcssXdciEn;
-/** Offset 0x09E0 - TCSS DMA0 Enable
+/** Offset 0x0A30 - TCSS DMA0 Enable
Set TCSS DMA0. 0:Disabled 1:Enabled
$EN_DIS
**/
UINT8 TcssDma0En;
-/** Offset 0x09E1 - TCSS DMA1 Enable
+/** Offset 0x0A31 - TCSS DMA1 Enable
Set TCSS DMA1. 0:Disabled 1:Enabled
$EN_DIS
**/
UINT8 TcssDma1En;
-/** Offset 0x09E2 - PcdSerialDebugBaudRate
+/** Offset 0x0A32 - PcdSerialDebugBaudRate
Baud Rate for Serial Debug Messages. 3:9600, 4:19200, 6:56700, 7:115200.
3:9600, 4:19200, 6:56700, 7:115200
**/
UINT8 PcdSerialDebugBaudRate;
-/** Offset 0x09E3 - HobBufferSize
+/** Offset 0x0A33 - HobBufferSize
Size to set HOB Buffer. 0:Default, 1: 1 Byte, 2: 1 KB, 3: Max value(assuming 63KB
total HOB size).
0:Default, 1: 1 Byte, 2: 1 KB, 3: Max value
**/
UINT8 HobBufferSize;
-/** Offset 0x09E4 - Early Command Training
+/** Offset 0x0A34 - Early Command Training
Enables/Disable Early Command Training
$EN_DIS
**/
UINT8 ECT;
-/** Offset 0x09E5 - SenseAmp Offset Training
+/** Offset 0x0A35 - SenseAmp Offset Training
Enables/Disable SenseAmp Offset Training
$EN_DIS
**/
UINT8 SOT;
-/** Offset 0x09E6 - Early ReadMPR Timing Centering 2D
+/** Offset 0x0A36 - Early ReadMPR Timing Centering 2D
Enables/Disable Early ReadMPR Timing Centering 2D
$EN_DIS
**/
UINT8 ERDMPRTC2D;
-/** Offset 0x09E7 - Read MPR Training
+/** Offset 0x0A37 - Read MPR Training
Enables/Disable Read MPR Training
$EN_DIS
**/
UINT8 RDMPRT;
-/** Offset 0x09E8 - Receive Enable Training
+/** Offset 0x0A38 - Receive Enable Training
Enables/Disable Receive Enable Training
$EN_DIS
**/
UINT8 RCVET;
-/** Offset 0x09E9 - Jedec Write Leveling
+/** Offset 0x0A39 - Jedec Write Leveling
Enables/Disable Jedec Write Leveling
$EN_DIS
**/
UINT8 JWRL;
-/** Offset 0x09EA - Early Write Time Centering 2D
+/** Offset 0x0A3A - Early Write Time Centering 2D
Enables/Disable Early Write Time Centering 2D
$EN_DIS
**/
UINT8 EWRTC2D;
-/** Offset 0x09EB - Early Read Time Centering 2D
+/** Offset 0x0A3B - Early Read Time Centering 2D
Enables/Disable Early Read Time Centering 2D
$EN_DIS
**/
UINT8 ERDTC2D;
-/** Offset 0x09EC - Reserved
+/** Offset 0x0A3C - Reserved
**/
- UINT8 Reserved45;
+ UINT8 Reserved46;
-/** Offset 0x09ED - Write Timing Centering 1D
+/** Offset 0x0A3D - Write Timing Centering 1D
Enables/Disable Write Timing Centering 1D
$EN_DIS
**/
UINT8 WRTC1D;
-/** Offset 0x09EE - Write Voltage Centering 1D
+/** Offset 0x0A3E - Write Voltage Centering 1D
Enables/Disable Write Voltage Centering 1D
$EN_DIS
**/
UINT8 WRVC1D;
-/** Offset 0x09EF - Read Timing Centering 1D
+/** Offset 0x0A3F - Read Timing Centering 1D
Enables/Disable Read Timing Centering 1D
$EN_DIS
**/
UINT8 RDTC1D;
-/** Offset 0x09F0 - Read Voltage Centering 1D
+/** Offset 0x0A40 - Read Voltage Centering 1D
Enable/Disable Read Voltage Centering 1D
$EN_DIS
**/
UINT8 RDVC1D;
-/** Offset 0x09F1 - Reserved
+/** Offset 0x0A41 - Reserved
**/
- UINT8 Reserved46[2];
+ UINT8 Reserved47[2];
-/** Offset 0x09F3 - Read ODT Training
+/** Offset 0x0A43 - Read ODT Training
Enables/Disable Read ODT Training
$EN_DIS
**/
UINT8 RDODTT;
-/** Offset 0x09F4 - Read Equalization Training
+/** Offset 0x0A44 - Read Equalization Training
Enables/Disable Read Equalization Training
$EN_DIS
**/
UINT8 RDEQT;
-/** Offset 0x09F5 - Reserved
+/** Offset 0x0A45 - Reserved
**/
- UINT8 Reserved47;
+ UINT8 Reserved48;
-/** Offset 0x09F6 - Write Timing Centering 2D
+/** Offset 0x0A46 - Write Timing Centering 2D
Enables/Disable Write Timing Centering 2D
$EN_DIS
**/
UINT8 WRTC2D;
-/** Offset 0x09F7 - Read Timing Centering 2D
+/** Offset 0x0A47 - Read Timing Centering 2D
Enables/Disable Read Timing Centering 2D
$EN_DIS
**/
UINT8 RDTC2D;
-/** Offset 0x09F8 - Write Voltage Centering 2D
+/** Offset 0x0A48 - Write Voltage Centering 2D
Enables/Disable Write Voltage Centering 2D
$EN_DIS
**/
UINT8 WRVC2D;
-/** Offset 0x09F9 - Read Voltage Centering 2D
+/** Offset 0x0A49 - Read Voltage Centering 2D
Enables/Disable Read Voltage Centering 2D
$EN_DIS
**/
UINT8 RDVC2D;
-/** Offset 0x09FA - Reserved
+/** Offset 0x0A4A - Reserved
**/
- UINT8 Reserved48;
+ UINT8 Reserved49;
-/** Offset 0x09FB - Command Voltage Centering
+/** Offset 0x0A4B - Command Voltage Centering
Enables/Disable Command Voltage Centering
$EN_DIS
**/
UINT8 CMDVC;
-/** Offset 0x09FC - Late Command Training
+/** Offset 0x0A4C - Late Command Training
Enables/Disable Late Command Training
$EN_DIS
**/
UINT8 LCT;
-/** Offset 0x09FD - Turn Around Timing Training
+/** Offset 0x0A4D - Turn Around Timing Training
Enables/Disable Turn Around Timing Training
$EN_DIS
**/
UINT8 TAT;
-/** Offset 0x09FE - Rank Margin Tool
+/** Offset 0x0A4E - Rank Margin Tool
Enable/disable Rank Margin Tool
$EN_DIS
**/
UINT8 RMT;
-/** Offset 0x09FF - Reserved
+/** Offset 0x0A4F - Reserved
**/
- UINT8 Reserved49;
+ UINT8 Reserved50;
-/** Offset 0x0A00 - DIMM SPD Alias Test
+/** Offset 0x0A50 - DIMM SPD Alias Test
Enables/Disable DIMM SPD Alias Test
$EN_DIS
**/
UINT8 ALIASCHK;
-/** Offset 0x0A01 - Retrain Margin Check
+/** Offset 0x0A51 - Retrain Margin Check
Enables/Disable Retrain Margin Check
$EN_DIS
**/
UINT8 RMC;
-/** Offset 0x0A02 - Reserved
+/** Offset 0x0A52 - Reserved
**/
- UINT8 Reserved50;
+ UINT8 Reserved51;
-/** Offset 0x0A03 - Dimm ODT Training
+/** Offset 0x0A53 - Dimm ODT Training
Enables/Disable Dimm ODT Training
$EN_DIS
**/
UINT8 DIMMODTT;
-/** Offset 0x0A04 - DIMM RON Training
+/** Offset 0x0A54 - DIMM RON Training
Enables/Disable DIMM RON Training
$EN_DIS
**/
UINT8 DIMMRONT;
-/** Offset 0x0A05 - TxDqTCO Comp Training
+/** Offset 0x0A55 - TxDqTCO Comp Training
Enable/Disable TxDqTCO Comp Training
$EN_DIS
**/
UINT8 TXTCO;
-/** Offset 0x0A06 - ClkTCO Comp Training
+/** Offset 0x0A56 - ClkTCO Comp Training
Enable/Disable ClkTCO Comp Training
$EN_DIS
**/
UINT8 CLKTCO;
-/** Offset 0x0A07 - CMD Slew Rate Training
+/** Offset 0x0A57 - CMD Slew Rate Training
Enable/Disable CMD Slew Rate Training
$EN_DIS
**/
UINT8 CMDSR;
-/** Offset 0x0A08 - Reserved
+/** Offset 0x0A58 - Reserved
**/
- UINT8 Reserved51[2];
+ UINT8 Reserved52[2];
-/** Offset 0x0A0A - DIMM CA ODT Training
+/** Offset 0x0A5A - DIMM CA ODT Training
Enable/Disable DIMM CA ODT Training
$EN_DIS
**/
UINT8 DIMMODTCA;
-/** Offset 0x0A0B - Reserved
+/** Offset 0x0A5B - Reserved
**/
- UINT8 Reserved52[3];
+ UINT8 Reserved53[3];
-/** Offset 0x0A0E - Read Vref Decap Training
+/** Offset 0x0A5E - Read Vref Decap Training
Enable/Disable Read Vref Decap Training
$EN_DIS
**/
UINT8 RDVREFDC;
-/** Offset 0x0A0F - Vddq Training
+/** Offset 0x0A5F - Vddq Training
Enable/Disable Vddq Training
$EN_DIS
**/
UINT8 VDDQT;
-/** Offset 0x0A10 - Rank Margin Tool Per Bit
+/** Offset 0x0A60 - Rank Margin Tool Per Bit
Enable/Disable Rank Margin Tool Per Bit
$EN_DIS
**/
UINT8 RMTBIT;
-/** Offset 0x0A11 - Reserved
+/** Offset 0x0A61 - Reserved
**/
- UINT8 Reserved53[4];
+ UINT8 Reserved54[4];
-/** Offset 0x0A15 - Duty Cycle Correction Training
+/** Offset 0x0A65 - Duty Cycle Correction Training
Enable/Disable Duty Cycle Correction Training
$EN_DIS
**/
UINT8 DCC;
-/** Offset 0x0A16 - Reserved
+/** Offset 0x0A66 - Reserved
**/
- UINT8 Reserved54[17];
+ UINT8 Reserved55[17];
-/** Offset 0x0A27 - ECC Support
+/** Offset 0x0A77 - ECC Support
Enables/Disable ECC Support
$EN_DIS
**/
UINT8 EccSupport;
-/** Offset 0x0A28 - Ibecc
+/** Offset 0x0A78 - Ibecc
In-Band ECC Support
$EN_DIS
**/
UINT8 Ibecc;
-/** Offset 0x0A29 - IbeccParity
+/** Offset 0x0A79 - IbeccParity
In-Band ECC Parity Control
$EN_DIS
**/
UINT8 IbeccParity;
-/** Offset 0x0A2A - IbeccOperationMode
+/** Offset 0x0A7A - IbeccOperationMode
In-Band ECC Operation Mode
0:Protect base on address range, 1: Non-protected, 2: All protected
**/
UINT8 IbeccOperationMode;
-/** Offset 0x0A2B - IbeccProtectedRegionEnable
+/** Offset 0x0A7B - IbeccProtectedRegionEnable
In-Band ECC Protected Region Enable
$EN_DIS
**/
UINT8 IbeccProtectedRegionEnable[8];
-/** Offset 0x0A33 - Reserved
+/** Offset 0x0A83 - Reserved
**/
- UINT8 Reserved55;
+ UINT8 Reserved56;
-/** Offset 0x0A34 - IbeccProtectedRegionBases
+/** Offset 0x0A84 - IbeccProtectedRegionBases
IBECC Protected Region Bases per IBECC instance
**/
UINT16 IbeccProtectedRegionBase[8];
-/** Offset 0x0A44 - IbeccProtectedRegionMasks
+/** Offset 0x0A94 - IbeccProtectedRegionMasks
IBECC Protected Region Masks
**/
UINT16 IbeccProtectedRegionMask[8];
-/** Offset 0x0A54 - IbeccProtectedRegionOverallBases
+/** Offset 0x0AA4 - IbeccProtectedRegionOverallBases
IBECC Protected Region Bases based on enabled IBECC instance
**/
UINT16 IbeccProtectedRegionOverallBase[8];
-/** Offset 0x0A64 - Memory Remap
+/** Offset 0x0AB4 - Memory Remap
Enables/Disable Memory Remap
$EN_DIS
**/
UINT8 RemapEnable;
-/** Offset 0x0A65 - Rank Interleave support
+/** Offset 0x0AB5 - Rank Interleave support
Enables/Disable Rank Interleave support. NOTE: RI and HORI can not be enabled at
the same time.
$EN_DIS
**/
UINT8 RankInterleave;
-/** Offset 0x0A66 - Enhanced Interleave support
+/** Offset 0x0AB6 - Enhanced Interleave support
Enables/Disable Enhanced Interleave support
$EN_DIS
**/
UINT8 EnhancedInterleave;
-/** Offset 0x0A67 - Ch Hash Support
+/** Offset 0x0AB7 - Ch Hash Support
Enable/Disable Channel Hash Support. NOTE: ONLY if Memory interleaved Mode
$EN_DIS
**/
UINT8 ChHashEnable;
-/** Offset 0x0A68 - Extern Therm Status
+/** Offset 0x0AB8 - Extern Therm Status
Enables/Disable Extern Therm Status
$EN_DIS
**/
UINT8 EnableExtts;
-/** Offset 0x0A69 - DDR PowerDown and idle counter
+/** Offset 0x0AB9 - DDR PowerDown and idle counter
Enables/Disable DDR PowerDown and idle counter(For LPDDR Only)
$EN_DIS
**/
UINT8 EnablePwrDn;
-/** Offset 0x0A6A - DDR PowerDown and idle counter
+/** Offset 0x0ABA - DDR PowerDown and idle counter
Enables/Disable DDR PowerDown and idle counter(For LPDDR Only)
$EN_DIS
**/
UINT8 EnablePwrDnLpddr;
-/** Offset 0x0A6B - SelfRefresh Enable
+/** Offset 0x0ABB - SelfRefresh Enable
Enables/Disable SelfRefresh Enable
$EN_DIS
**/
UINT8 SrefCfgEna;
-/** Offset 0x0A6C - Throttler CKEMin Defeature
+/** Offset 0x0ABC - Throttler CKEMin Defeature
Enables/Disable Throttler CKEMin Defeature(For LPDDR Only)
$EN_DIS
**/
UINT8 ThrtCkeMinDefeatLpddr;
-/** Offset 0x0A6D - Throttler CKEMin Defeature
+/** Offset 0x0ABD - Throttler CKEMin Defeature
Enables/Disable Throttler CKEMin Defeature
$EN_DIS
**/
UINT8 ThrtCkeMinDefeat;
-/** Offset 0x0A6E - Reserved
+/** Offset 0x0ABE - Reserved
**/
- UINT8 Reserved56;
+ UINT8 Reserved57;
-/** Offset 0x0A6F - Exit On Failure (MRC)
+/** Offset 0x0ABF - Exit On Failure (MRC)
Enables/Disable Exit On Failure (MRC)
$EN_DIS
**/
UINT8 ExitOnFailure;
-/** Offset 0x0A70 - Reserved
+/** Offset 0x0AC0 - Reserved
**/
- UINT8 Reserved57[4];
+ UINT8 Reserved58[4];
-/** Offset 0x0A74 - Select if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP
+/** Offset 0x0AC4 - Select if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP
ESelect if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP
$EN_DIS
**/
UINT8 Ddr4DdpSharedZq;
-/** Offset 0x0A75 - Ch Hash Interleaved Bit
+/** Offset 0x0AC5 - Ch Hash Interleaved Bit
Select the BIT to be used for Channel Interleaved mode. NOTE: BIT7 will interlave
the channels at a 2 cacheline granularity, BIT8 at 4 and BIT9 at 8. Default is BIT8
0:BIT6, 1:BIT7, 2:BIT8, 3:BIT9, 4:BIT10, 5:BIT11, 6:BIT12, 7:BIT13
**/
UINT8 ChHashInterleaveBit;
-/** Offset 0x0A76 - Ch Hash Mask
+/** Offset 0x0AC6 - Ch Hash Mask
Set the BIT(s) to be included in the XOR function. NOTE BIT mask corresponds to
BITS [19:6] Default is 0x30CC
**/
UINT16 ChHashMask;
-/** Offset 0x0A78 - Base reference clock value
+/** Offset 0x0AC8 - Base reference clock value
Base reference clock value, in Hertz(Default is 125Hz)
100000000:100Hz, 125000000:125Hz, 167000000:167Hz, 250000000:250Hz
**/
UINT32 BClkFrequency;
-/** Offset 0x0A7C - EPG DIMM Idd3N
+/** Offset 0x0ACC - EPG DIMM Idd3N
Active standby current (Idd3N) in milliamps from datasheet. Must be calculated on
a per DIMM basis. Default is 26
**/
UINT16 Idd3n;
-/** Offset 0x0A7E - EPG DIMM Idd3P
+/** Offset 0x0ACE - EPG DIMM Idd3P
Active power-down current (Idd3P) in milliamps from datasheet. Must be calculated
on a per DIMM basis. Default is 11
**/
UINT16 Idd3p;
-/** Offset 0x0A80 - CMD Normalization
+/** Offset 0x0AD0 - CMD Normalization
Enable/Disable CMD Normalization
$EN_DIS
**/
UINT8 CMDNORM;
-/** Offset 0x0A81 - Early DQ Write Drive Strength and Equalization Training
+/** Offset 0x0AD1 - Early DQ Write Drive Strength and Equalization Training
Enable/Disable Early DQ Write Drive Strength and Equalization Training
$EN_DIS
**/
UINT8 EWRDSEQ;
-/** Offset 0x0A82 - Idle Energy Mc0Ch0Dimm0
+/** Offset 0x0AD2 - Idle Energy Mc0Ch0Dimm0
Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)
**/
UINT8 IdleEnergyMc0Ch0Dimm0;
-/** Offset 0x0A83 - Idle Energy Mc0Ch0Dimm1
+/** Offset 0x0AD3 - Idle Energy Mc0Ch0Dimm1
Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)
**/
UINT8 IdleEnergyMc0Ch0Dimm1;
-/** Offset 0x0A84 - Idle Energy Mc0Ch1Dimm0
+/** Offset 0x0AD4 - Idle Energy Mc0Ch1Dimm0
Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)
**/
UINT8 IdleEnergyMc0Ch1Dimm0;
-/** Offset 0x0A85 - Idle Energy Mc0Ch1Dimm1
+/** Offset 0x0AD5 - Idle Energy Mc0Ch1Dimm1
Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)
**/
UINT8 IdleEnergyMc0Ch1Dimm1;
-/** Offset 0x0A86 - Idle Energy Mc1Ch0Dimm0
+/** Offset 0x0AD6 - Idle Energy Mc1Ch0Dimm0
Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)
**/
UINT8 IdleEnergyMc1Ch0Dimm0;
-/** Offset 0x0A87 - Idle Energy Mc1Ch0Dimm1
+/** Offset 0x0AD7 - Idle Energy Mc1Ch0Dimm1
Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)
**/
UINT8 IdleEnergyMc1Ch0Dimm1;
-/** Offset 0x0A88 - Idle Energy Mc1Ch1Dimm0
+/** Offset 0x0AD8 - Idle Energy Mc1Ch1Dimm0
Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)
**/
UINT8 IdleEnergyMc1Ch1Dimm0;
-/** Offset 0x0A89 - Idle Energy Mc1Ch1Dimm1
+/** Offset 0x0AD9 - Idle Energy Mc1Ch1Dimm1
Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)
**/
UINT8 IdleEnergyMc1Ch1Dimm1;
-/** Offset 0x0A8A - PowerDown Energy Mc0Ch0Dimm0
+/** Offset 0x0ADA - PowerDown Energy Mc0Ch0Dimm0
PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def)
**/
UINT8 PdEnergyMc0Ch0Dimm0;
-/** Offset 0x0A8B - PowerDown Energy Mc0Ch0Dimm1
+/** Offset 0x0ADB - PowerDown Energy Mc0Ch0Dimm1
PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def)
**/
UINT8 PdEnergyMc0Ch0Dimm1;
-/** Offset 0x0A8C - PowerDown Energy Mc0Ch1Dimm0
+/** Offset 0x0ADC - PowerDown Energy Mc0Ch1Dimm0
PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def)
**/
UINT8 PdEnergyMc0Ch1Dimm0;
-/** Offset 0x0A8D - PowerDown Energy Mc0Ch1Dimm1
+/** Offset 0x0ADD - PowerDown Energy Mc0Ch1Dimm1
PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def)
**/
UINT8 PdEnergyMc0Ch1Dimm1;
-/** Offset 0x0A8E - PowerDown Energy Mc1Ch0Dimm0
+/** Offset 0x0ADE - PowerDown Energy Mc1Ch0Dimm0
PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def)
**/
UINT8 PdEnergyMc1Ch0Dimm0;
-/** Offset 0x0A8F - PowerDown Energy Mc1Ch0Dimm1
+/** Offset 0x0ADF - PowerDown Energy Mc1Ch0Dimm1
PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def)
**/
UINT8 PdEnergyMc1Ch0Dimm1;
-/** Offset 0x0A90 - PowerDown Energy Mc1Ch1Dimm0
+/** Offset 0x0AE0 - PowerDown Energy Mc1Ch1Dimm0
PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def)
**/
UINT8 PdEnergyMc1Ch1Dimm0;
-/** Offset 0x0A91 - PowerDown Energy Mc1Ch1Dimm1
+/** Offset 0x0AE1 - PowerDown Energy Mc1Ch1Dimm1
PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def)
**/
UINT8 PdEnergyMc1Ch1Dimm1;
-/** Offset 0x0A92 - Activate Energy Mc0Ch0Dimm0
+/** Offset 0x0AE2 - Activate Energy Mc0Ch0Dimm0
Activate Energy Contribution, range[255;0],(172= Def)
**/
UINT8 ActEnergyMc0Ch0Dimm0;
-/** Offset 0x0A93 - Activate Energy Mc0Ch0Dimm1
+/** Offset 0x0AE3 - Activate Energy Mc0Ch0Dimm1
Activate Energy Contribution, range[255;0],(172= Def)
**/
UINT8 ActEnergyMc0Ch0Dimm1;
-/** Offset 0x0A94 - Activate Energy Mc0Ch1Dimm0
+/** Offset 0x0AE4 - Activate Energy Mc0Ch1Dimm0
Activate Energy Contribution, range[255;0],(172= Def)
**/
UINT8 ActEnergyMc0Ch1Dimm0;
-/** Offset 0x0A95 - Activate Energy Mc0Ch1Dimm1
+/** Offset 0x0AE5 - Activate Energy Mc0Ch1Dimm1
Activate Energy Contribution, range[255;0],(172= Def)
**/
UINT8 ActEnergyMc0Ch1Dimm1;
-/** Offset 0x0A96 - Activate Energy Mc1Ch0Dimm0
+/** Offset 0x0AE6 - Activate Energy Mc1Ch0Dimm0
Activate Energy Contribution, range[255;0],(172= Def)
**/
UINT8 ActEnergyMc1Ch0Dimm0;
-/** Offset 0x0A97 - Activate Energy Mc1Ch0Dimm1
+/** Offset 0x0AE7 - Activate Energy Mc1Ch0Dimm1
Activate Energy Contribution, range[255;0],(172= Def)
**/
UINT8 ActEnergyMc1Ch0Dimm1;
-/** Offset 0x0A98 - Activate Energy Mc1Ch1Dimm0
+/** Offset 0x0AE8 - Activate Energy Mc1Ch1Dimm0
Activate Energy Contribution, range[255;0],(172= Def)
**/
UINT8 ActEnergyMc1Ch1Dimm0;
-/** Offset 0x0A99 - Activate Energy Mc1Ch1Dimm1
+/** Offset 0x0AE9 - Activate Energy Mc1Ch1Dimm1
Activate Energy Contribution, range[255;0],(172= Def)
**/
UINT8 ActEnergyMc1Ch1Dimm1;
-/** Offset 0x0A9A - Read Energy Mc0Ch0Dimm0
+/** Offset 0x0AEA - Read Energy Mc0Ch0Dimm0
Read Energy Contribution, range[255;0],(212= Def)
**/
UINT8 RdEnergyMc0Ch0Dimm0;
-/** Offset 0x0A9B - Read Energy Mc0Ch0Dimm1
+/** Offset 0x0AEB - Read Energy Mc0Ch0Dimm1
Read Energy Contribution, range[255;0],(212= Def)
**/
UINT8 RdEnergyMc0Ch0Dimm1;
-/** Offset 0x0A9C - Read Energy Mc0Ch1Dimm0
+/** Offset 0x0AEC - Read Energy Mc0Ch1Dimm0
Read Energy Contribution, range[255;0],(212= Def)
**/
UINT8 RdEnergyMc0Ch1Dimm0;
-/** Offset 0x0A9D - Read Energy Mc0Ch1Dimm1
+/** Offset 0x0AED - Read Energy Mc0Ch1Dimm1
Read Energy Contribution, range[255;0],(212= Def)
**/
UINT8 RdEnergyMc0Ch1Dimm1;
-/** Offset 0x0A9E - Read Energy Mc1Ch0Dimm0
+/** Offset 0x0AEE - Read Energy Mc1Ch0Dimm0
Read Energy Contribution, range[255;0],(212= Def)
**/
UINT8 RdEnergyMc1Ch0Dimm0;
-/** Offset 0x0A9F - Read Energy Mc1Ch0Dimm1
+/** Offset 0x0AEF - Read Energy Mc1Ch0Dimm1
Read Energy Contribution, range[255;0],(212= Def)
**/
UINT8 RdEnergyMc1Ch0Dimm1;
-/** Offset 0x0AA0 - Read Energy Mc1Ch1Dimm0
+/** Offset 0x0AF0 - Read Energy Mc1Ch1Dimm0
Read Energy Contribution, range[255;0],(212= Def)
**/
UINT8 RdEnergyMc1Ch1Dimm0;
-/** Offset 0x0AA1 - Read Energy Mc1Ch1Dimm1
+/** Offset 0x0AF1 - Read Energy Mc1Ch1Dimm1
Read Energy Contribution, range[255;0],(212= Def)
**/
UINT8 RdEnergyMc1Ch1Dimm1;
-/** Offset 0x0AA2 - Write Energy Mc0Ch0Dimm0
+/** Offset 0x0AF2 - Write Energy Mc0Ch0Dimm0
Write Energy Contribution, range[255;0],(221= Def)
**/
UINT8 WrEnergyMc0Ch0Dimm0;
-/** Offset 0x0AA3 - Write Energy Mc0Ch0Dimm1
+/** Offset 0x0AF3 - Write Energy Mc0Ch0Dimm1
Write Energy Contribution, range[255;0],(221= Def)
**/
UINT8 WrEnergyMc0Ch0Dimm1;
-/** Offset 0x0AA4 - Write Energy Mc0Ch1Dimm0
+/** Offset 0x0AF4 - Write Energy Mc0Ch1Dimm0
Write Energy Contribution, range[255;0],(221= Def)
**/
UINT8 WrEnergyMc0Ch1Dimm0;
-/** Offset 0x0AA5 - Write Energy Mc0Ch1Dimm1
+/** Offset 0x0AF5 - Write Energy Mc0Ch1Dimm1
Write Energy Contribution, range[255;0],(221= Def)
**/
UINT8 WrEnergyMc0Ch1Dimm1;
-/** Offset 0x0AA6 - Write Energy Mc1Ch0Dimm0
+/** Offset 0x0AF6 - Write Energy Mc1Ch0Dimm0
Write Energy Contribution, range[255;0],(221= Def)
**/
UINT8 WrEnergyMc1Ch0Dimm0;
-/** Offset 0x0AA7 - Write Energy Mc1Ch0Dimm1
+/** Offset 0x0AF7 - Write Energy Mc1Ch0Dimm1
Write Energy Contribution, range[255;0],(221= Def)
**/
UINT8 WrEnergyMc1Ch0Dimm1;
-/** Offset 0x0AA8 - Write Energy Mc1Ch1Dimm0
+/** Offset 0x0AF8 - Write Energy Mc1Ch1Dimm0
Write Energy Contribution, range[255;0],(221= Def)
**/
UINT8 WrEnergyMc1Ch1Dimm0;
-/** Offset 0x0AA9 - Write Energy Mc1Ch1Dimm1
+/** Offset 0x0AF9 - Write Energy Mc1Ch1Dimm1
Write Energy Contribution, range[255;0],(221= Def)
**/
UINT8 WrEnergyMc1Ch1Dimm1;
-/** Offset 0x0AAA - Throttler CKEMin Timer
+/** Offset 0x0AFA - Throttler CKEMin Timer
Timer value for CKEMin, range[255;0]. Req'd min of SC_ROUND_T + BYTE_LENGTH (4).
Dfault is 0x00
**/
UINT8 ThrtCkeMinTmr;
-/** Offset 0x0AAB - Reserved
+/** Offset 0x0AFB - Reserved
**/
- UINT8 Reserved58[2];
+ UINT8 Reserved59[2];
-/** Offset 0x0AAD - Rapl Power Floor Ch0
+/** Offset 0x0AFD - Rapl Power Floor Ch0
Power budget ,range[255;0],(0= 5.3W Def)
**/
UINT8 RaplPwrFlCh0;
-/** Offset 0x0AAE - Rapl Power Floor Ch1
+/** Offset 0x0AFE - Rapl Power Floor Ch1
Power budget ,range[255;0],(0= 5.3W Def)
**/
UINT8 RaplPwrFlCh1;
-/** Offset 0x0AAF - Command Rate Support
+/** Offset 0x0AFF - Command Rate Support
CMD Rate and Limit Support Option. NOTE: ONLY supported in 1N Mode, Default is 3 CMDs
0:Disable, 5:2 CMDS, 7:3 CMDS, 9:4 CMDS, 11:5 CMDS, 13:6 CMDS, 15:7 CMDS
**/
UINT8 EnCmdRate;
-/** Offset 0x0AB0 - Reserved
+/** Offset 0x0B00 - Reserved
**/
- UINT8 Reserved59;
+ UINT8 Reserved60;
-/** Offset 0x0AB1 - Energy Performance Gain
+/** Offset 0x0B01 - Energy Performance Gain
Enable/disable Energy Performance Gain. <b>0: Disable</b>; 1: Enable
$EN_DIS
**/
UINT8 EpgEnable;
-/** Offset 0x0AB2 - Reserved
+/** Offset 0x0B02 - Reserved
**/
- UINT8 Reserved60;
+ UINT8 Reserved61;
-/** Offset 0x0AB3 - User Manual Threshold
+/** Offset 0x0B03 - User Manual Threshold
Disabled: Predefined threshold will be used.\n
Enabled: User Input will be used.
$EN_DIS
**/
UINT8 UserThresholdEnable;
-/** Offset 0x0AB4 - User Manual Budget
+/** Offset 0x0B04 - User Manual Budget
Disabled: Configuration of memories will defined the Budget value.\n
Enabled: User Input will be used.
$EN_DIS
**/
UINT8 UserBudgetEnable;
-/** Offset 0x0AB5 - Power Down Mode
+/** Offset 0x0B05 - Power Down Mode
This option controls command bus tristating during idle periods
0x0:No Power Down, 0x1:APD, 0x6:PPD DLL OFF, 0xFF:Auto
**/
UINT8 PowerDownMode;
-/** Offset 0x0AB6 - Pwr Down Idle Timer
+/** Offset 0x0B06 - Pwr Down Idle Timer
The minimum value should = to the worst case Roundtrip delay + Burst_Length. 0 means
AUTO: 64 for ULX/ULT, 128 for DT/Halo
**/
UINT8 PwdwnIdleCounter;
-/** Offset 0x0AB7 - Page Close Idle Timeout
+/** Offset 0x0B07 - Page Close Idle Timeout
This option controls Page Close Idle Timeout
0:Enabled, 1:Disabled
**/
UINT8 DisPgCloseIdleTimeout;
-/** Offset 0x0AB8 - Bitmask of ranks that have CA bus terminated
+/** Offset 0x0B08 - Bitmask of ranks that have CA bus terminated
Offset 225 LPDDR4: Bitmask of ranks that have CA bus terminated. <b>0x01=Default,
Rank0 is terminating and Rank1 is non-terminating</b>
**/
UINT8 CmdRanksTerminated;
-/** Offset 0x0AB9 - PcdSerialDebugLevel
+/** Offset 0x0B09 - PcdSerialDebugLevel
Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load,
Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings,
Info & Verbose.
@@ -2670,72 +2668,72 @@ typedef struct {
**/
UINT8 PcdSerialDebugLevel;
-/** Offset 0x0ABA - Reserved
+/** Offset 0x0B0A - Reserved
**/
- UINT8 Reserved61[7];
+ UINT8 Reserved62[7];
-/** Offset 0x0AC1 - Ask MRC to clear memory content
+/** Offset 0x0B11 - Ask MRC to clear memory content
Ask MRC to clear memory content <b>0: Do not Clear Memory;</b> 1: Clear Memory.
$EN_DIS
**/
UINT8 CleanMemory;
-/** Offset 0x0AC2 - TCSS USB Port Enable
+/** Offset 0x0B12 - TCSS USB Port Enable
Bitmap for per port enabling
**/
UINT8 UsbTcPortEnPreMem;
-/** Offset 0x0AC3 - Reserved
+/** Offset 0x0B13 - Reserved
**/
- UINT8 Reserved62;
+ UINT8 Reserved63;
-/** Offset 0x0AC4 - Post Code Output Port
+/** Offset 0x0B14 - Post Code Output Port
This option configures Post Code Output Port
**/
UINT16 PostCodeOutputPort;
-/** Offset 0x0AC6 - RMTLoopCount
+/** Offset 0x0B16 - RMTLoopCount
Specifies the Loop Count to be used during Rank Margin Tool Testing. 0 - AUTO
**/
UINT8 RMTLoopCount;
-/** Offset 0x0AC7 - Enable/Disable SA CRID
+/** Offset 0x0B17 - Enable/Disable SA CRID
Enable: SA CRID, Disable (Default): SA CRID
$EN_DIS
**/
UINT8 CridEnable;
-/** Offset 0x0AC8 - BCLK RFI Frequency
+/** Offset 0x0B18 - BCLK RFI Frequency
Bclk RFI Frequency for each SAGV point in Hz units. 98000000Hz = 98MHz <b>0 - No
RFI Tuning</b>. Range is 98Mhz-100Mhz.
**/
UINT32 BclkRfiFreq[4];
-/** Offset 0x0AD8 - Size of PCIe IMR.
+/** Offset 0x0B28 - Size of PCIe IMR.
Size of PCIe IMR in megabytes
**/
UINT16 PcieImrSize;
-/** Offset 0x0ADA - Enable PCIe IMR
+/** Offset 0x0B2A - Enable PCIe IMR
0: Disable(AUTO), 1: Enable
$EN_DIS
**/
UINT8 PcieImrEnabled;
-/** Offset 0x0ADB - Enable PCIe IMR
+/** Offset 0x0B2B - Enable PCIe IMR
1: PCH PCIE, 2: SA PCIE. If PCIeImrEnabled is TRUE then this will use to select
the Root port location from PCH PCIe or SA PCIe
$EN_DIS
**/
UINT8 PcieImrRpLocation;
-/** Offset 0x0ADC - Root port number for IMR.
+/** Offset 0x0B2C - Root port number for IMR.
Root port number for IMR.If PCieImrRpLocation is PCH PCIe then select root port
from 0 to 23 and if it is SA PCIe then select root port from 0 to 3
**/
UINT8 PcieImrRpSelection;
-/** Offset 0x0ADD - SerialDebugMrcLevel
+/** Offset 0x0B2D - SerialDebugMrcLevel
MRC Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load,
Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings,
Info & Verbose.
@@ -2744,208 +2742,208 @@ typedef struct {
**/
UINT8 SerialDebugMrcLevel;
-/** Offset 0x0ADE - Reserved
+/** Offset 0x0B2E - Reserved
**/
- UINT8 Reserved63[13];
+ UINT8 Reserved64[13];
-/** Offset 0x0AEB - Command Pins Mapping
+/** Offset 0x0B3B - Command Pins Mapping
BitMask where bits [3:0] are Controller 0 Channel [3:0] and bits [7:4] are Controller
1 Channel [3:0]. 0 = CCC pin mapping is Ascending, 1 = CCC pin mapping is Descending.
**/
UINT8 Lp5CccConfig;
-/** Offset 0x0AEC - Command Pins Mirrored
+/** Offset 0x0B3C - Command Pins Mirrored
BitMask where bits [3:0] are Controller 0 Channel [3:0] and bits [7:4] are Controller
1 Channel [3:0]. 0 = No Command Mirror and 1 = Command Mirror.
**/
UINT8 CmdMirror;
-/** Offset 0x0AED - Reserved
+/** Offset 0x0B3D - Reserved
**/
- UINT8 Reserved64[4];
+ UINT8 Reserved65[4];
-/** Offset 0x0AF1 - Skip external display device scanning
+/** Offset 0x0B41 - Skip external display device scanning
Enable: Do not scan for external display device, Disable (Default): Scan external
display devices
$EN_DIS
**/
UINT8 SkipExtGfxScan;
-/** Offset 0x0AF2 - Generate BIOS Data ACPI Table
+/** Offset 0x0B42 - Generate BIOS Data ACPI Table
Enable: Generate BDAT for MRC RMT or SA PCIe data. Disable (Default): Do not generate it
$EN_DIS
**/
UINT8 BdatEnable;
-/** Offset 0x0AF3 - Lock PCU Thermal Management registers
+/** Offset 0x0B43 - Lock PCU Thermal Management registers
Lock PCU Thermal Management registers. Enable(Default)=1, Disable=0
$EN_DIS
**/
UINT8 LockPTMregs;
-/** Offset 0x0AF4 - Panel Power Enable
+/** Offset 0x0B44 - Panel Power Enable
Control for enabling/disabling VDD force bit (Required only for early enabling of
eDP panel). 0=Disable, 1(Default)=Enable
$EN_DIS
**/
UINT8 PanelPowerEnable;
-/** Offset 0x0AF5 - BdatTestType
+/** Offset 0x0B45 - BdatTestType
Indicates the type of Memory Training data to populate into the BDAT ACPI table.
0:RMT per Rank, 1:RMT per Bit, 2:Margin2D
**/
UINT8 BdatTestType;
-/** Offset 0x0AF6 - Reserved
+/** Offset 0x0B46 - Reserved
**/
- UINT8 Reserved65[2];
+ UINT8 Reserved66[2];
-/** Offset 0x0AF8 - PMR Size
+/** Offset 0x0B48 - PMR Size
Size of PMR memory buffer. 0x400000 for normal boot and 0x200000 for S3 boot
**/
UINT32 DmaBufferSize;
-/** Offset 0x0AFC - The policy for VTd driver behavior
+/** Offset 0x0B4C - The policy for VTd driver behavior
BIT0: Enable IOMMU during boot, BIT1: Enable IOMMU when transfer control to OS
**/
UINT8 PreBootDmaMask;
-/** Offset 0x0AFD - Reserved
+/** Offset 0x0B4D - Reserved
**/
- UINT8 Reserved66[95];
+ UINT8 Reserved67[95];
-/** Offset 0x0B5C - TotalFlashSize
+/** Offset 0x0BAC - TotalFlashSize
Enable/Disable. 0: Disable, define default value of TotalFlashSize , 1: enable
**/
UINT16 TotalFlashSize;
-/** Offset 0x0B5E - BiosSize
+/** Offset 0x0BAE - BiosSize
The size of the BIOS region of the IFWI. Used if FspmUpd->FspmConfig.BiosGuard !=
0. If BiosGuard is enabled, MRC will increase the size of the DPR (DMA Protected
Range) so that a BIOS Update Script can be stored in the DPR.
**/
UINT16 BiosSize;
-/** Offset 0x0B60 - Reserved
+/** Offset 0x0BB0 - Reserved
**/
- UINT8 Reserved67[12];
+ UINT8 Reserved68[12];
-/** Offset 0x0B6C - Smbus dynamic power gating
+/** Offset 0x0BBC - Smbus dynamic power gating
Disable or Enable Smbus dynamic power gating.
$EN_DIS
**/
UINT8 SmbusDynamicPowerGating;
-/** Offset 0x0B6D - Disable and Lock Watch Dog Register
+/** Offset 0x0BBD - Disable and Lock Watch Dog Register
Set 1 to clear WDT status, then disable and lock WDT registers.
$EN_DIS
**/
UINT8 WdtDisableAndLock;
-/** Offset 0x0B6E - SMBUS SPD Write Disable
+/** Offset 0x0BBE - SMBUS SPD Write Disable
Set/Clear Smbus SPD Write Disable. 0: leave SPD Write Disable bit; 1: set SPD Write
Disable bit. For security recommendations, SPD write disable bit must be set.
$EN_DIS
**/
UINT8 SmbusSpdWriteDisable;
-/** Offset 0x0B6F - Reserved
+/** Offset 0x0BBF - Reserved
**/
- UINT8 Reserved68[34];
+ UINT8 Reserved69[34];
-/** Offset 0x0B91 - HECI Timeouts
+/** Offset 0x0BE1 - HECI Timeouts
0: Disable, 1: Enable (Default) timeout check for HECI
$EN_DIS
**/
UINT8 HeciTimeouts;
-/** Offset 0x0B92 - Force ME DID Init Status
+/** Offset 0x0BE2 - Force ME DID Init Status
Test, 0: disable, 1: Success, 2: No Memory in Channels, 3: Memory Init Error, Set
ME DID init stat value
$EN_DIS
**/
UINT8 DidInitStat;
-/** Offset 0x0B93 - CPU Replaced Polling Disable
+/** Offset 0x0BE3 - CPU Replaced Polling Disable
Test, 0: disable, 1: enable, Setting this option disables CPU replacement polling loop
$EN_DIS
**/
UINT8 DisableCpuReplacedPolling;
-/** Offset 0x0B94 - Check HECI message before send
+/** Offset 0x0BE4 - Check HECI message before send
Test, 0: disable, 1: enable, Enable/Disable message check.
$EN_DIS
**/
UINT8 DisableMessageCheck;
-/** Offset 0x0B95 - Skip MBP HOB
+/** Offset 0x0BE5 - Skip MBP HOB
Test, 0: disable, 1: enable, Enable/Disable MOB HOB.
$EN_DIS
**/
UINT8 SkipMbpHob;
-/** Offset 0x0B96 - HECI2 Interface Communication
+/** Offset 0x0BE6 - HECI2 Interface Communication
Test, 0: disable, 1: enable, Adds or Removes HECI2 Device from PCI space.
$EN_DIS
**/
UINT8 HeciCommunication2;
-/** Offset 0x0B97 - Enable KT device
+/** Offset 0x0BE7 - Enable KT device
Test, 0: disable, 1: enable, Enable or Disable KT device.
$EN_DIS
**/
UINT8 KtDeviceEnable;
-/** Offset 0x0B98 - Skip CPU replacement check
+/** Offset 0x0BE8 - Skip CPU replacement check
Test, 0: disable, 1: enable, Setting this option to skip CPU replacement check
$EN_DIS
**/
UINT8 SkipCpuReplacementCheck;
-/** Offset 0x0B99 - Avx2 Voltage Guardband Scaling Factor
+/** Offset 0x0BE9 - Avx2 Voltage Guardband Scaling Factor
AVX2 Voltage Guardband Scale factor applied to AVX2 workloads. Range is 0-200 in
1/100 units, where a value of 125 would apply a 1.25 scale factor.
**/
UINT8 Avx2VoltageScaleFactor;
-/** Offset 0x0B9A - Avx512 Voltage Guardband Scaling Factor
+/** Offset 0x0BEA - Avx512 Voltage Guardband Scaling Factor
AVX512 Voltage Guardband Scale factor applied to AVX512 workloads. Range is 0-200
in 1/100 units, where a value of 125 would apply a 1.25 scale factor.
**/
UINT8 Avx512VoltageScaleFactor;
-/** Offset 0x0B9B - Serial Io Uart Debug Mode
+/** Offset 0x0BEB - Serial Io Uart Debug Mode
Select SerialIo Uart Controller mode
0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom,
4:SerialIoUartSkipInit
**/
UINT8 SerialIoUartDebugMode;
-/** Offset 0x0B9C - SerialIoUartDebugRxPinMux - FSPM
+/** Offset 0x0BEC - SerialIoUartDebugRxPinMux - FSPM
Select RX pin muxing for SerialIo UART used for debug
**/
UINT32 SerialIoUartDebugRxPinMux;
-/** Offset 0x0BA0 - SerialIoUartDebugTxPinMux - FSPM
+/** Offset 0x0BF0 - SerialIoUartDebugTxPinMux - FSPM
Select TX pin muxing for SerialIo UART used for debug
**/
UINT32 SerialIoUartDebugTxPinMux;
-/** Offset 0x0BA4 - SerialIoUartDebugRtsPinMux - FSPM
+/** Offset 0x0BF4 - SerialIoUartDebugRtsPinMux - FSPM
Select SerialIo Uart used for debug Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS*
for possible values.
**/
UINT32 SerialIoUartDebugRtsPinMux;
-/** Offset 0x0BA8 - SerialIoUartDebugCtsPinMux - FSPM
+/** Offset 0x0BF8 - SerialIoUartDebugCtsPinMux - FSPM
Select SerialIo Uart used for debug Cts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_CTS*
for possible values.
**/
UINT32 SerialIoUartDebugCtsPinMux;
-/** Offset 0x0BAC - Reserved
+/** Offset 0x0BFC - Reserved
**/
- UINT8 Reserved69[20];
+ UINT8 Reserved70[20];
} FSP_M_CONFIG;
/** Fsp M UPD Configuration
@@ -2964,11 +2962,11 @@ typedef struct {
**/
FSP_M_CONFIG FspmConfig;
-/** Offset 0x0BC0
+/** Offset 0x0C10
**/
UINT8 Rsvd500[6];
-/** Offset 0x0BC6
+/** Offset 0x0C16
**/
UINT16 UpdTerminator;
} FSPM_UPD;
diff --git a/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspsUpd.h
index f4fca766ad..f9401293fb 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspsUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspsUpd.h
@@ -138,7 +138,7 @@ typedef struct {
UINT32 MicrocodeRegionSize;
/** Offset 0x0060 - Turbo Mode
- Enable/Disable processor Turbo Mode. <b>0:disable</b>, 1: Enable
+ Enable/Disable processor Turbo Mode. 0:disable, <b>1: Enable</b>
$EN_DIS
**/
UINT8 TurboMode;
@@ -997,31 +997,25 @@ typedef struct {
**/
UINT16 WatchDogTimerBios;
-/** Offset 0x0516 - Force MEBX execution
- Enable/Disable. 0: Disable, 1: enable, Force MEBX execution.
- $EN_DIS
-**/
- UINT8 ForcMebxSyncUp;
-
-/** Offset 0x0517 - PCH PCIe root port connection type
+/** Offset 0x0516 - PCH PCIe root port connection type
0: built-in device, 1:slot
**/
UINT8 PcieRpSlotImplemented[29];
-/** Offset 0x0534 - PCIE RP Access Control Services Extended Capability
+/** Offset 0x0533 - PCIE RP Access Control Services Extended Capability
Enable/Disable PCIE RP Access Control Services Extended Capability
**/
UINT8 PcieRpAcsEnabled[29];
-/** Offset 0x0551 - PCIE RP Clock Power Management
+/** Offset 0x0550 - PCIE RP Clock Power Management
Enable/Disable PCIE RP Clock Power Management, even if disabled, CLKREQ# signal
can still be controlled by L1 PM substates mechanism
**/
UINT8 PcieRpEnableCpm[29];
-/** Offset 0x056E - Reserved
+/** Offset 0x056D - Reserved
**/
- UINT8 Reserved22[2];
+ UINT8 Reserved22[3];
/** Offset 0x0570 - PCIE RP Detect Timeout Ms
The number of milliseconds within 0~65535 in reference code will wait for link to
@@ -2222,74 +2216,74 @@ typedef struct {
/** Offset 0x1A56 - Reserved
**/
- UINT8 Reserved52[48];
+ UINT8 Reserved52[99];
-/** Offset 0x1A86 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3
+/** Offset 0x1AB9 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3
Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3, Each
value in array can be between 0-1. One byte for each port.
**/
UINT8 Usb3HsioTxRate3UniqTranEnable[10];
-/** Offset 0x1A90 - USB 3.0 TX Output Unique Transition Bit Scale for rate 3
+/** Offset 0x1AC3 - USB 3.0 TX Output Unique Transition Bit Scale for rate 3
USB 3.0 TX Output Unique Transition Bit Scale for rate 3, HSIO_TX_DWORD9[6:0], <b>Default
= 4Ch</b>. One byte for each port.
**/
UINT8 Usb3HsioTxRate3UniqTran[10];
-/** Offset 0x1A9A - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 2
+/** Offset 0x1ACD - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 2
Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 2, Each
value in array can be between 0-1. One byte for each port.
**/
UINT8 Usb3HsioTxRate2UniqTranEnable[10];
-/** Offset 0x1AA4 - USB 3.0 TX Output Unique Transition Bit Scale for rate 2
+/** Offset 0x1AD7 - USB 3.0 TX Output Unique Transition Bit Scale for rate 2
USB 3.0 TX Output Unique Transition Bit Scale for rate 2, HSIO_TX_DWORD9[14:8],
<b>Default = 4Ch</b>. One byte for each port.
**/
UINT8 Usb3HsioTxRate2UniqTran[10];
-/** Offset 0x1AAE - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 1
+/** Offset 0x1AE1 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 1
Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 1, Each
value in array can be between 0-1. One byte for each port.
**/
UINT8 Usb3HsioTxRate1UniqTranEnable[10];
-/** Offset 0x1AB8 - USB 3.0 TX Output Unique Transition Bit Scale for rate 1
+/** Offset 0x1AEB - USB 3.0 TX Output Unique Transition Bit Scale for rate 1
USB 3.0 TX Output Unique Transition Bit Scale for rate 1, HSIO_TX_DWORD9[22:16],
<b>Default = 4Ch</b>. One byte for each port.
**/
UINT8 Usb3HsioTxRate1UniqTran[10];
-/** Offset 0x1AC2 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 0
+/** Offset 0x1AF5 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 0
Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 0, Each
value in array can be between 0-1. One byte for each port.
**/
UINT8 Usb3HsioTxRate0UniqTranEnable[10];
-/** Offset 0x1ACC - USB 3.0 TX Output Unique Transition Bit Scale for rate 0
+/** Offset 0x1AFF - USB 3.0 TX Output Unique Transition Bit Scale for rate 0
USB 3.0 TX Output Unique Transition Bit Scale for rate 0, HSIO_TX_DWORD9[30:24],
<b>Default = 4Ch</b>. One byte for each port.
**/
UINT8 Usb3HsioTxRate0UniqTran[10];
-/** Offset 0x1AD6 - Skip PAM regsiter lock
+/** Offset 0x1B09 - Skip PAM regsiter lock
Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default):
PAM registers will be locked by RC
$EN_DIS
**/
UINT8 SkipPamLock;
-/** Offset 0x1AD7 - Enable/Disable IGFX RenderStandby
+/** Offset 0x1B0A - Enable/Disable IGFX RenderStandby
Enable(Default): Enable IGFX RenderStandby, Disable: Disable IGFX RenderStandby
$EN_DIS
**/
UINT8 RenderStandby;
-/** Offset 0x1AD8 - Reserved
+/** Offset 0x1B0B - Reserved
**/
UINT8 Reserved53;
-/** Offset 0x1AD9 - GT Frequency Limit
+/** Offset 0x1B0C - GT Frequency Limit
0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz,
7: 350 Mhz, 8: 400 Mhz, 9: 450 Mhz, 0xA: 500 Mhz, 0xB: 550 Mhz, 0xC: 600 Mhz, 0xD:
650 Mhz, 0xE: 700 Mhz, 0xF: 750 Mhz, 0x10: 800 Mhz, 0x11: 850 Mhz, 0x12:900 Mhz,
@@ -2303,51 +2297,51 @@ typedef struct {
**/
UINT8 GtFreqMax;
-/** Offset 0x1ADA - Disable Turbo GT
+/** Offset 0x1B0D - Disable Turbo GT
0=Disable: GT frequency is not limited, 1=Enable: Disables Turbo GT frequency
$EN_DIS
**/
UINT8 DisableTurboGt;
-/** Offset 0x1ADB - Reserved
+/** Offset 0x1B0E - Reserved
**/
UINT8 Reserved54[2];
-/** Offset 0x1ADD - Enable TSN Multi-VC
+/** Offset 0x1B10 - Enable TSN Multi-VC
Enable/disable Multi Virtual Channels(VC) in TSN.
$EN_DIS
**/
UINT8 PchTsnMultiVcEnable;
-/** Offset 0x1ADE - Reserved
+/** Offset 0x1B11 - Reserved
**/
- UINT8 Reserved55[2];
+ UINT8 Reserved55[3];
-/** Offset 0x1AE0 - LogoPixelHeight Address
+/** Offset 0x1B14 - LogoPixelHeight Address
Address of LogoPixelHeight
**/
UINT32 LogoPixelHeight;
-/** Offset 0x1AE4 - LogoPixelWidth Address
+/** Offset 0x1B18 - LogoPixelWidth Address
Address of LogoPixelWidth
**/
UINT32 LogoPixelWidth;
-/** Offset 0x1AE8 - Reserved
+/** Offset 0x1B1C - Reserved
**/
UINT8 Reserved56[45];
-/** Offset 0x1B15 - RSR feature
+/** Offset 0x1B49 - RSR feature
Enable or Disable RSR feature; 0: Disable; <b>1: Enable </b>
$EN_DIS
**/
UINT8 EnableRsr;
-/** Offset 0x1B16 - Reserved
+/** Offset 0x1B4A - Reserved
**/
UINT8 Reserved57[4];
-/** Offset 0x1B1A - Enable or Disable HWP
+/** Offset 0x1B4E - Enable or Disable HWP
Enable/Disable Intel(R) Speed Shift Technology support. Enabling will expose the
CPPC v2 interface to allow for hardware controlled P-states. 0: Disable; <b>1:
Enable;</b>
@@ -2355,7 +2349,7 @@ typedef struct {
**/
UINT8 Hwp;
-/** Offset 0x1B1B - Package Long duration turbo mode time
+/** Offset 0x1B4F - Package Long duration turbo mode time
Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0
= default value (28 sec for Mobile and 8 sec for Desktop). Defines time window
which Processor Base Power (TDP) value should be maintained. Valid values(Unit
@@ -2364,14 +2358,14 @@ typedef struct {
**/
UINT8 PowerLimit1Time;
-/** Offset 0x1B1C - Short Duration Turbo Mode
+/** Offset 0x1B50 - Short Duration Turbo Mode
Enable/Disable Power Limit 2 override. If this option is disabled, BIOS will program
the default values for Power Limit 2. 0: Disable; <b>1: Enable</b>
$EN_DIS
**/
UINT8 PowerLimit2;
-/** Offset 0x1B1D - Turbo settings Lock
+/** Offset 0x1B51 - Turbo settings Lock
Enable/Disable locking of Package Power Limit settings. When enabled, PACKAGE_POWER_LIMIT
MSR will be locked and a reset will be required to unlock the register. <b>0: Disable;
</b> 1: Enable
@@ -2379,7 +2373,7 @@ typedef struct {
**/
UINT8 TurboPowerLimitLock;
-/** Offset 0x1B1E - Package PL3 time window
+/** Offset 0x1B52 - Package PL3 time window
Power Limit 3 Time Window value in Milli seconds. Indicates the time window over
which Power Limit 3 value should be maintained. If the value is 0, BIOS leaves
the hardware default value. Valid value: <b>0</b>, 3-8, 10, 12, 14, 16, 20, 24,
@@ -2387,108 +2381,108 @@ typedef struct {
**/
UINT8 PowerLimit3Time;
-/** Offset 0x1B1F - Package PL3 Duty Cycle
+/** Offset 0x1B53 - Package PL3 Duty Cycle
Specify the duty cycle in percentage that the CPU is required to maintain over the
configured time window. Range is 0-100.
**/
UINT8 PowerLimit3DutyCycle;
-/** Offset 0x1B20 - Package PL3 Lock
+/** Offset 0x1B54 - Package PL3 Lock
Power Limit 3 Lock. When enabled PL3 configurations are locked during OS. When disabled
PL3 configuration can be changed during OS. <b>0: Disable</b> ; 1:Enable
$EN_DIS
**/
UINT8 PowerLimit3Lock;
-/** Offset 0x1B21 - Package PL4 Lock
+/** Offset 0x1B55 - Package PL4 Lock
Power Limit 4 Lock. When enabled PL4 configurations are locked during OS. When disabled
PL4 configuration can be changed during OS. <b>0: Disable</b> ; 1:Enable
$EN_DIS
**/
UINT8 PowerLimit4Lock;
-/** Offset 0x1B22 - TCC Activation Offset
+/** Offset 0x1B56 - TCC Activation Offset
TCC Activation Offset. Offset from factory set TCC activation temperature at which
the Thermal Control Circuit must be activated. TCC will be activated at TCC Activation
Temperature, in volts. <b>Default = 0h</b>.
**/
UINT8 TccActivationOffset;
-/** Offset 0x1B23 - Tcc Offset Clamp Enable/Disable
+/** Offset 0x1B57 - Tcc Offset Clamp Enable/Disable
Tcc Offset Clamp for Runtime Average Temperature Limit (RATL) allows CPU to throttle
below P1. <b>0: Disabled</b>; 1: Enabled.
$EN_DIS
**/
UINT8 TccOffsetClamp;
-/** Offset 0x1B24 - Tcc Offset Lock
+/** Offset 0x1B58 - Tcc Offset Lock
Tcc Offset Lock for Runtime Average Temperature Limit (RATL) to lock temperature
target; <b>0: Disabled</b>; 1: Enabled.
$EN_DIS
**/
UINT8 TccOffsetLock;
-/** Offset 0x1B25 - Custom Ratio State Entries
+/** Offset 0x1B59 - Custom Ratio State Entries
The number of custom ratio state entries, ranges from 0 to 40 for a valid custom
ratio table. Sets the number of custom P-states. At least 2 states must be present
**/
UINT8 NumberOfEntries;
-/** Offset 0x1B26 - Custom Short term Power Limit time window
+/** Offset 0x1B5A - Custom Short term Power Limit time window
Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0
= default value (28 sec for Mobile and 8 sec for Desktop). Defines time window
which Processor Base Power (TDP) value should be maintained.
**/
UINT8 Custom1PowerLimit1Time;
-/** Offset 0x1B27 - Custom Turbo Activation Ratio
+/** Offset 0x1B5B - Custom Turbo Activation Ratio
Custom value for Turbo Activation Ratio. Needs to be configured with valid values
from LFM to Max Turbo. 0 means don't use custom value. Valid Range 0 to 255
**/
UINT8 Custom1TurboActivationRatio;
-/** Offset 0x1B28 - Custom Config Tdp Control
+/** Offset 0x1B5C - Custom Config Tdp Control
Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2
**/
UINT8 Custom1ConfigTdpControl;
-/** Offset 0x1B29 - Custom Short term Power Limit time window
+/** Offset 0x1B5D - Custom Short term Power Limit time window
Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0
= default value (28 sec for Mobile and 8 sec for Desktop). Defines time window
which Processor Base Power (TDP) value should be maintained.
**/
UINT8 Custom2PowerLimit1Time;
-/** Offset 0x1B2A - Custom Turbo Activation Ratio
+/** Offset 0x1B5E - Custom Turbo Activation Ratio
Custom value for Turbo Activation Ratio. Needs to be configured with valid values
from LFM to Max Turbo. 0 means don't use custom value. Valid Range 0 to 255
**/
UINT8 Custom2TurboActivationRatio;
-/** Offset 0x1B2B - Custom Config Tdp Control
+/** Offset 0x1B5F - Custom Config Tdp Control
Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2
**/
UINT8 Custom2ConfigTdpControl;
-/** Offset 0x1B2C - Custom Short term Power Limit time window
+/** Offset 0x1B60 - Custom Short term Power Limit time window
Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0
= default value (28 sec for Mobile and 8 sec for Desktop). Defines time window
which Processor Base Power (TDP) value should be maintained.
**/
UINT8 Custom3PowerLimit1Time;
-/** Offset 0x1B2D - Custom Turbo Activation Ratio
+/** Offset 0x1B61 - Custom Turbo Activation Ratio
Custom value for Turbo Activation Ratio. Needs to be configured with valid values
from LFM to Max Turbo. 0 means don't use custom value. Valid Range 0 to 255
**/
UINT8 Custom3TurboActivationRatio;
-/** Offset 0x1B2E - Custom Config Tdp Control
+/** Offset 0x1B62 - Custom Config Tdp Control
Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2
**/
UINT8 Custom3ConfigTdpControl;
-/** Offset 0x1B2F - ConfigTdp mode settings Lock
+/** Offset 0x1B63 - ConfigTdp mode settings Lock
Configurable Processor Base Power (cTDP) Mode Lock sets the Lock bits on TURBO_ACTIVATION_RATIO
and CONFIG_TDP_CONTROL. Note: When CTDP Lock is enabled Custom ConfigTDP Count
will be forced to 1 and Custom ConfigTDP Boot Index will be forced to 0. <b>0:
@@ -2497,7 +2491,7 @@ typedef struct {
**/
UINT8 ConfigTdpLock;
-/** Offset 0x1B30 - Load Configurable TDP SSDT
+/** Offset 0x1B64 - Load Configurable TDP SSDT
Enables Configurable Processor Base Power (cTDP) control via runtime ACPI BIOS methods.
This 'BIOS only' feature does not require EC or driver support. <b>0: Disable</b>;
1: Enable.
@@ -2505,7 +2499,7 @@ typedef struct {
**/
UINT8 ConfigTdpBios;
-/** Offset 0x1B31 - PL1 Enable value
+/** Offset 0x1B65 - PL1 Enable value
Enable/Disable Platform Power Limit 1 programming. If this option is enabled, it
activates the PL1 value to be used by the processor to limit the average power
of given time window. <b>0: Disable</b>; 1: Enable.
@@ -2513,7 +2507,7 @@ typedef struct {
**/
UINT8 PsysPowerLimit1;
-/** Offset 0x1B32 - PL1 timewindow
+/** Offset 0x1B66 - PL1 timewindow
Platform Power Limit 1 Time Window value in seconds. The value may vary from 0 to
128. 0 = default values. Indicates the time window over which Platform Processor
Base Power (TDP) value should be maintained. Valid values(Unit in seconds) 0 to
@@ -2521,7 +2515,7 @@ typedef struct {
**/
UINT8 PsysPowerLimit1Time;
-/** Offset 0x1B33 - PL2 Enable Value
+/** Offset 0x1B67 - PL2 Enable Value
Enable/Disable Platform Power Limit 2 programming. If this option is disabled, BIOS
will program the default values for Platform Power Limit 2. <b>0: Disable</b>;
1: Enable.
@@ -2529,57 +2523,57 @@ typedef struct {
**/
UINT8 PsysPowerLimit2;
-/** Offset 0x1B34 - Enable or Disable MLC Streamer Prefetcher
+/** Offset 0x1B68 - Enable or Disable MLC Streamer Prefetcher
Enable or Disable MLC Streamer Prefetcher; 0: Disable; <b>1: Enable</b>.
$EN_DIS
**/
UINT8 MlcStreamerPrefetcher;
-/** Offset 0x1B35 - Enable or Disable MLC Spatial Prefetcher
+/** Offset 0x1B69 - Enable or Disable MLC Spatial Prefetcher
Enable or Disable MLC Spatial Prefetcher; 0: Disable; <b>1: Enable</b>
$EN_DIS
**/
UINT8 MlcSpatialPrefetcher;
-/** Offset 0x1B36 - Enable or Disable Monitor /MWAIT instructions
+/** Offset 0x1B6A - Enable or Disable Monitor /MWAIT instructions
Enable/Disable MonitorMWait, if Disable MonitorMwait, the AP threads Idle Manner
should not set in MWAIT Loop. 0: Disable; <b>1: Enable</b>.
$EN_DIS
**/
UINT8 MonitorMwaitEnable;
-/** Offset 0x1B37 - Enable or Disable initialization of machine check registers
+/** Offset 0x1B6B - Enable or Disable initialization of machine check registers
Enable or Disable initialization of machine check registers; 0: Disable; <b>1: Enable</b>.
$EN_DIS
**/
UINT8 MachineCheckEnable;
-/** Offset 0x1B38 - AP Idle Manner of waiting for SIPI
+/** Offset 0x1B6C - AP Idle Manner of waiting for SIPI
AP threads Idle Manner for waiting signal to run. 1: HALT loop; <b>2: MWAIT loop</b>;
3: RUN loop.
1: HALT loop, 2: MWAIT loop, 3: RUN loop
**/
UINT8 ApIdleManner;
-/** Offset 0x1B39 - Control on Processor Trace output scheme
+/** Offset 0x1B6D - Control on Processor Trace output scheme
Control on Processor Trace output scheme; <b>0: Single Range Output</b>; 1: ToPA Output.
0: Single Range Output, 1: ToPA Output
**/
UINT8 ProcessorTraceOutputScheme;
-/** Offset 0x1B3A - Enable or Disable Processor Trace feature
+/** Offset 0x1B6E - Enable or Disable Processor Trace feature
Enable or Disable Processor Trace feature; <b>0: Disable</b>; 1: Enable.
$EN_DIS
**/
UINT8 ProcessorTraceEnable;
-/** Offset 0x1B3B - Enable or Disable Intel SpeedStep Technology
+/** Offset 0x1B6F - Enable or Disable Intel SpeedStep Technology
Allows more than two frequency ranges to be supported. 0: Disable; <b>1: Enable</b>
$EN_DIS
**/
UINT8 Eist;
-/** Offset 0x1B3C - Enable or Disable Energy Efficient P-state
+/** Offset 0x1B70 - Enable or Disable Energy Efficient P-state
Enable/Disable Energy Efficient P-state feature. When set to 0, will disable access
to ENERGY_PERFORMANCE_BIAS MSR and CPUID Function will read 0 indicating no support
for Energy Efficient policy setting. When set to 1 will enable access to ENERGY_PERFORMANCE_BIAS
@@ -2589,7 +2583,7 @@ typedef struct {
**/
UINT8 EnergyEfficientPState;
-/** Offset 0x1B3D - Enable or Disable Energy Efficient Turbo
+/** Offset 0x1B71 - Enable or Disable Energy Efficient Turbo
Enable/Disable Energy Efficient Turbo Feature. This feature will opportunistically
lower the turbo frequency to increase efficiency. Recommended only to disable in
overclocking situations where turbo frequency must remain constant. Otherwise,
@@ -2598,100 +2592,100 @@ typedef struct {
**/
UINT8 EnergyEfficientTurbo;
-/** Offset 0x1B3E - Enable or Disable T states
+/** Offset 0x1B72 - Enable or Disable T states
Enable or Disable T states; <b>0: Disable</b>; 1: Enable.
$EN_DIS
**/
UINT8 TStates;
-/** Offset 0x1B3F - Enable or Disable Bi-Directional PROCHOT#
+/** Offset 0x1B73 - Enable or Disable Bi-Directional PROCHOT#
Enable or Disable Bi-Directional PROCHOT#; 0: Disable; <b>1: Enable</b>
$EN_DIS
**/
UINT8 BiProcHot;
-/** Offset 0x1B40 - Enable or Disable PROCHOT# signal being driven externally
+/** Offset 0x1B74 - Enable or Disable PROCHOT# signal being driven externally
Enable or Disable PROCHOT# signal being driven externally; 0: Disable; <b>1: Enable</b>.
$EN_DIS
**/
UINT8 DisableProcHotOut;
-/** Offset 0x1B41 - Enable or Disable PROCHOT# Response
+/** Offset 0x1B75 - Enable or Disable PROCHOT# Response
Enable or Disable PROCHOT# Response; <b>0: Disable</b>; 1: Enable.
$EN_DIS
**/
UINT8 ProcHotResponse;
-/** Offset 0x1B42 - Enable or Disable VR Thermal Alert
+/** Offset 0x1B76 - Enable or Disable VR Thermal Alert
Enable or Disable VR Thermal Alert; <b>0: Disable</b>; 1: Enable.
$EN_DIS
**/
UINT8 DisableVrThermalAlert;
-/** Offset 0x1B43 - Enable or Disable Thermal Reporting
+/** Offset 0x1B77 - Enable or Disable Thermal Reporting
Enable or Disable Thermal Reporting through ACPI tables; 0: Disable; <b>1: Enable</b>.
$EN_DIS
**/
UINT8 EnableAllThermalFunctions;
-/** Offset 0x1B44 - Enable or Disable Thermal Monitor
+/** Offset 0x1B78 - Enable or Disable Thermal Monitor
Enable or Disable Thermal Monitor; 0: Disable; <b>1: Enable</b>
$EN_DIS
**/
UINT8 ThermalMonitor;
-/** Offset 0x1B45 - Enable or Disable CPU power states (C-states)
+/** Offset 0x1B79 - Enable or Disable CPU power states (C-states)
Enable/Disable CPU Power Management. Allows CPU to go to C states when it's not
100% utilized. 0: Disable; <b>1: Enable</b>
$EN_DIS
**/
UINT8 Cx;
-/** Offset 0x1B46 - Configure C-State Configuration Lock
+/** Offset 0x1B7A - Configure C-State Configuration Lock
Configure MSR to CFG Lock bit. 0: Disable; <b>1: Enable</b>.
$EN_DIS
**/
UINT8 PmgCstCfgCtrlLock;
-/** Offset 0x1B47 - Enable or Disable Enhanced C-states
+/** Offset 0x1B7B - Enable or Disable Enhanced C-states
Enable/Disable C1E. When enabled, CPU will switch to minimum speed when all cores
enter C-State. 0: Disable; <b>1: Enable</b>
$EN_DIS
**/
UINT8 C1e;
-/** Offset 0x1B48 - Enable or Disable Package Cstate Demotion
+/** Offset 0x1B7C - Enable or Disable Package Cstate Demotion
Enable or Disable Package C-State Demotion. 0: Disable; <b>1: Enable</b>
$EN_DIS
**/
UINT8 PkgCStateDemotion;
-/** Offset 0x1B49 - Enable or Disable Package Cstate UnDemotion
+/** Offset 0x1B7D - Enable or Disable Package Cstate UnDemotion
Enable or Disable Package C-State Un-Demotion. 0: Disable; <b>1: Enable</b>
$EN_DIS
**/
UINT8 PkgCStateUnDemotion;
-/** Offset 0x1B4A - Enable or Disable CState-Pre wake
+/** Offset 0x1B7E - Enable or Disable CState-Pre wake
Disable - to disable the Cstate Pre-Wake. 0: Disable; <b>1: Enable</b>
$EN_DIS
**/
UINT8 CStatePreWake;
-/** Offset 0x1B4B - Enable or Disable TimedMwait Support.
+/** Offset 0x1B7F - Enable or Disable TimedMwait Support.
Enable or Disable TimedMwait Support. <b>0: Disable</b>; 1: Enable
$EN_DIS
**/
UINT8 TimedMwait;
-/** Offset 0x1B4C - Enable or Disable IO to MWAIT redirection
+/** Offset 0x1B80 - Enable or Disable IO to MWAIT redirection
When set, will map IO_read instructions sent to IO registers PMG_IO_BASE_ADDRBASE+offset
to MWAIT(offset). <b>0: Disable</b>; 1: Enable.
$EN_DIS
**/
UINT8 CstCfgCtrIoMwaitRedirection;
-/** Offset 0x1B4D - Set the Max Pkg Cstate
+/** Offset 0x1B81 - Set the Max Pkg Cstate
Maximum Package C State Limit Setting. Cpu Default: Leaves to Factory default value.
Auto: Initializes to deepest available Package C State Limit. Valid values 0 -
C0/C1, 1 - C2, 2 - C3, 3 - C6, 4 - C7, 5 - C7S, 6 - C8, 7 - C9, 8 - C10, 254 -
@@ -2699,38 +2693,38 @@ typedef struct {
**/
UINT8 PkgCStateLimit;
-/** Offset 0x1B4E - Interrupt Redirection Mode Select
+/** Offset 0x1B82 - Interrupt Redirection Mode Select
Interrupt Redirection Mode Select for Logical Interrupts. 0: Fixed priority; 1:
Round robin; 2: Hash vector; 7: No change.
**/
UINT8 PpmIrmSetting;
-/** Offset 0x1B4F - Lock prochot configuration
+/** Offset 0x1B83 - Lock prochot configuration
Lock prochot configuration Enable/Disable; 0: Disable;<b> 1: Enable</b>
$EN_DIS
**/
UINT8 ProcHotLock;
-/** Offset 0x1B50 - Configuration for boot TDP selection
+/** Offset 0x1B84 - Configuration for boot TDP selection
Configurable Processor Base Power (cTDP) Mode as Nominal/Level1/Level2/Deactivate
TDP selection. Deactivate option will set MSR to Nominal and MMIO to Zero. <b>0:
TDP Nominal</b>; 1: TDP Down; 2: TDP Up;0xFF : Deactivate
**/
UINT8 ConfigTdpLevel;
-/** Offset 0x1B51 - Max P-State Ratio
+/** Offset 0x1B85 - Max P-State Ratio
Maximum P-state ratio to use in the custom P-state table. Valid Range 0 to 0x7F
**/
UINT8 MaxRatio;
-/** Offset 0x1B52 - P-state ratios for custom P-state table
+/** Offset 0x1B86 - P-state ratios for custom P-state table
P-state ratios for custom P-state table. NumberOfEntries has valid range between
0 to 40. For no. of P-States supported(NumberOfEntries) , StateRatio[NumberOfEntries]
are configurable. Valid Range of each entry is 0 to 0x7F
**/
UINT8 StateRatio[40];
-/** Offset 0x1B7A - P-state ratios for max 16 version of custom P-state table
+/** Offset 0x1BAE - P-state ratios for max 16 version of custom P-state table
P-state ratios for max 16 version of custom P-state table. This table is used for
OS versions limited to a max of 16 P-States. If the first entry of this table is
0, or if Number of Entries is 16 or less, then this table will be ignored, and
@@ -2739,11 +2733,11 @@ typedef struct {
**/
UINT8 StateRatioMax16[16];
-/** Offset 0x1B8A - Reserved
+/** Offset 0x1BBE - Reserved
**/
UINT8 Reserved58[2];
-/** Offset 0x1B8C - Package Long duration turbo mode power limit
+/** Offset 0x1BC0 - Package Long duration turbo mode power limit
Power Limit 1 in Milli Watts. BIOS will round to the nearest 1/8W when programming.
Value set 120 = 15W. 0 = no custom override. Overclocking SKU: Value must be between
Max and Min Power Limits. Other SKUs: This value must be between Min Power Limit
@@ -2753,7 +2747,7 @@ typedef struct {
**/
UINT32 PowerLimit1;
-/** Offset 0x1B90 - Package Short duration turbo mode power limit
+/** Offset 0x1BC4 - Package Short duration turbo mode power limit
Power Limit 2 in Milli Watts. BIOS will round to the nearest 1/8W when programming.
Value set 120 = 15W. If the value is 0, BIOS will program this value as 1.25*Processor
Base Power (TDP). Processor applies control policies such that the package power
@@ -2762,7 +2756,7 @@ typedef struct {
**/
UINT32 PowerLimit2Power;
-/** Offset 0x1B94 - Package PL3 power limit
+/** Offset 0x1BC8 - Package PL3 power limit
Power Limit 3 in Milli Watts. BIOS will round to the nearest 1/8W when programming.
Value set 120 = 15W. XE SKU: Any value can be programmed. Overclocking SKU: Value
must be between Max and Min Power Limits. Other SKUs: This value must be between
@@ -2772,22 +2766,22 @@ typedef struct {
**/
UINT32 PowerLimit3;
-/** Offset 0x1B98 - Package PL4 power limit
+/** Offset 0x1BCC - Package PL4 power limit
Power Limit 4 in Milli Watts. BIOS will round to the nearest 1/8W when programming.
Value set 120 = 15W. If the value is 0, BIOS leaves default value. Units are based
on POWER_MGMT_CONFIG.CustomPowerUnit. Valid Range 0 to 32767.
**/
UINT32 PowerLimit4;
-/** Offset 0x1B9C - Reserved
+/** Offset 0x1BD0 - Reserved
**/
UINT8 Reserved59[4];
-/** Offset 0x1BA0 - Tcc Offset Time Window for RATL
+/** Offset 0x1BD4 - Tcc Offset Time Window for RATL
**/
UINT32 TccOffsetTimeWindowForRatl;
-/** Offset 0x1BA4 - Short term Power Limit value for custom cTDP level 1
+/** Offset 0x1BD8 - Short term Power Limit value for custom cTDP level 1
Power Limit 1 in Milli Watts. BIOS will round to the nearest 1/8W when programming.
Value set 120 = 15W. 0 = no custom override. Overclocking SKU: Value must be between
Max and Min Power Limits. Other SKUs: This value must be between Min Power Limit
@@ -2796,7 +2790,7 @@ typedef struct {
**/
UINT32 Custom1PowerLimit1;
-/** Offset 0x1BA8 - Long term Power Limit value for custom cTDP level 1
+/** Offset 0x1BDC - Long term Power Limit value for custom cTDP level 1
Power Limit 2 value in Milli Watts. BIOS will round to the nearest 1/8W when programming.
Value set 120 = 15W. 0 = no custom override. Processor applies control policies
such that the package power does not exceed this limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.
@@ -2804,7 +2798,7 @@ typedef struct {
**/
UINT32 Custom1PowerLimit2;
-/** Offset 0x1BAC - Short term Power Limit value for custom cTDP level 2
+/** Offset 0x1BE0 - Short term Power Limit value for custom cTDP level 2
Power Limit 1 in Milli Watts. BIOS will round to the nearest 1/8W when programming.
Value set 120 = 15W. 0 = no custom override. Overclocking SKU: Value must be between
Max and Min Power Limits. Other SKUs: This value must be between Min Power Limit
@@ -2813,7 +2807,7 @@ typedef struct {
**/
UINT32 Custom2PowerLimit1;
-/** Offset 0x1BB0 - Long term Power Limit value for custom cTDP level 2
+/** Offset 0x1BE4 - Long term Power Limit value for custom cTDP level 2
Power Limit 2 value in Milli Watts. BIOS will round to the nearest 1/8W when programming.
Value set 120 = 15W. 0 = no custom override. Processor applies control policies
such that the package power does not exceed this limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.
@@ -2821,7 +2815,7 @@ typedef struct {
**/
UINT32 Custom2PowerLimit2;
-/** Offset 0x1BB4 - Short term Power Limit value for custom cTDP level 3
+/** Offset 0x1BE8 - Short term Power Limit value for custom cTDP level 3
Power Limit 1 in Milli Watts. BIOS will round to the nearest 1/8W when programming.
Value set 120 = 15W. 0 = no custom override. Overclocking SKU: Value must be between
Max and Min Power Limits. Other SKUs: This value must be between Min Power Limit
@@ -2830,7 +2824,7 @@ typedef struct {
**/
UINT32 Custom3PowerLimit1;
-/** Offset 0x1BB8 - Long term Power Limit value for custom cTDP level 3
+/** Offset 0x1BEC - Long term Power Limit value for custom cTDP level 3
Power Limit 2 value in Milli Watts. BIOS will round to the nearest 1/8W when programming.
Value set 120 = 15W. 0 = no custom override. Processor applies control policies
such that the package power does not exceed this limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.
@@ -2838,7 +2832,7 @@ typedef struct {
**/
UINT32 Custom3PowerLimit2;
-/** Offset 0x1BBC - Platform PL1 power
+/** Offset 0x1BF0 - Platform PL1 power
Platform Power Limit 1 Power in Milli Watts. BIOS will round to the nearest 1/8W
when programming. Value set 120 = 15W. Any value can be programmed between Max
and Min Power Limits. This setting will act as the new PL1 value for the Package
@@ -2847,7 +2841,7 @@ typedef struct {
**/
UINT32 PsysPowerLimit1Power;
-/** Offset 0x1BC0 - Platform PL2 power
+/** Offset 0x1BF4 - Platform PL2 power
Platform Power Limit 2 Power in Milli Watts. BIOS will round to the nearest 1/8W
when programming. Value set 120 = 15W. Any value can be programmed between Max
and Min Power Limits. This setting will act as the new PL2 value for the Package
@@ -2856,11 +2850,11 @@ typedef struct {
**/
UINT32 PsysPowerLimit2Power;
-/** Offset 0x1BC4 - Reserved
+/** Offset 0x1BF8 - Reserved
**/
UINT8 Reserved60;
-/** Offset 0x1BC5 - Race To Halt
+/** Offset 0x1BF9 - Race To Halt
Enable/Disable Race To Halt feature. RTH will dynamically increase CPU frequency
in order to enter pkg C-State faster to reduce overall power. 0: Disable; <b>1:
Enable</b>
@@ -2868,66 +2862,66 @@ typedef struct {
**/
UINT8 RaceToHalt;
-/** Offset 0x1BC6 - Reserved
+/** Offset 0x1BFA - Reserved
**/
UINT8 Reserved61;
-/** Offset 0x1BC7 - Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT
+/** Offset 0x1BFB - Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT
Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT; <b>0: Disable</b>; 1: Enable.
$EN_DIS
**/
UINT8 HwpInterruptControl;
-/** Offset 0x1BC8 - Reserved
+/** Offset 0x1BFC - Reserved
**/
UINT8 Reserved62[4];
-/** Offset 0x1BCC - Intel Turbo Boost Max Technology 3.0
+/** Offset 0x1C00 - Intel Turbo Boost Max Technology 3.0
Enable/Disable Intel(R) Turbo Boost Max Technology 3.0 support. Disabling will report
the maximum ratio of the slowest core in _CPC object. 0: Disabled; <b>1: Enabled</b>
$EN_DIS
**/
UINT8 EnableItbm;
-/** Offset 0x1BCD - Enable or Disable C1 Cstate Demotion
+/** Offset 0x1C01 - Enable or Disable C1 Cstate Demotion
Enable or Disable C1 Cstate Auto Demotion. Disable; <b>1: Enable</b>
$EN_DIS
**/
UINT8 C1StateAutoDemotion;
-/** Offset 0x1BCE - Enable or Disable C1 Cstate UnDemotion
+/** Offset 0x1C02 - Enable or Disable C1 Cstate UnDemotion
Enable or Disable C1 Cstate Un-Demotion. Disable; <b>1: Enable</b>
$EN_DIS
**/
UINT8 C1StateUnDemotion;
-/** Offset 0x1BCF - Minimum Ring ratio limit override
+/** Offset 0x1C03 - Minimum Ring ratio limit override
Minimum Ring ratio limit override. <b>0: Hardware defaults.</b> Range: 0 - Max turbo
ratio limit
**/
UINT8 MinRingRatioLimit;
-/** Offset 0x1BD0 - Maximum Ring ratio limit override
+/** Offset 0x1C04 - Maximum Ring ratio limit override
Maximum Ring ratio limit override. <b>0: Hardware defaults.</b> Range: 0 - Max turbo
ratio limit
**/
UINT8 MaxRingRatioLimit;
-/** Offset 0x1BD1 - Enable or Disable Per Core P State OS control
+/** Offset 0x1C05 - Enable or Disable Per Core P State OS control
Enable/Disable Per Core P state OS control mode. When set, the highest core request
is used for all other core requests. 0: Disable; <b>1: Enable</b>
$EN_DIS
**/
UINT8 EnablePerCorePState;
-/** Offset 0x1BD2 - Enable or Disable HwP Autonomous Per Core P State OS control
+/** Offset 0x1C06 - Enable or Disable HwP Autonomous Per Core P State OS control
Disable Autonomous PCPS Autonomous will request the same value for all cores all
the time. 0: Disable; <b>1: Enable</b>
$EN_DIS
**/
UINT8 EnableHwpAutoPerCorePstate;
-/** Offset 0x1BD3 - Enable or Disable HwP Autonomous EPP Grouping
+/** Offset 0x1C07 - Enable or Disable HwP Autonomous EPP Grouping
Enable EPP grouping Autonomous will request the same values for all cores with same
EPP. Disable EPP grouping autonomous will not necessarily request same values for
all cores with same EPP. <b> 0: Disable </b>; 1: Enable
@@ -2935,7 +2929,7 @@ typedef struct {
**/
UINT8 EnableHwpAutoEppGrouping;
-/** Offset 0x1BD4 - Enable Configurable TDP
+/** Offset 0x1C08 - Enable Configurable TDP
Applies Configurable Processor Base Power (cTDP) initialization settings based on
non-cTDP or cTDP. Default is 1: Applies to cTDP; if 0 then applies non-cTDP and
BIOS will bypass cTDP initialzation flow
@@ -2943,42 +2937,42 @@ typedef struct {
**/
UINT8 ApplyConfigTdp;
-/** Offset 0x1BD5 - Reserved
+/** Offset 0x1C09 - Reserved
**/
UINT8 Reserved63;
-/** Offset 0x1BD6 - Dual Tau Boost
+/** Offset 0x1C0A - Dual Tau Boost
Enable Dual Tau Boost feature. This is only applicable for Desktop 35W/65W/125W
sku. When DPTF is enabled this feature is ignored. <b>0: Disable</b>; 1: Enable
$EN_DIS
**/
UINT8 DualTauBoost;
-/** Offset 0x1BD7 - Reserved
+/** Offset 0x1C0B - Reserved
**/
UINT8 Reserved64[31];
-/** Offset 0x1BF6 - End of Post message
+/** Offset 0x1C2A - End of Post message
Test, Send End of Post message. Disable(0x0): Disable EOP message, Send in PEI(0x1):
EOP send in PEI, Send in DXE(0x2)(Default): EOP send in DXE
0:Disable, 1:Send in PEI, 2:Send in DXE, 3:Reserved
**/
UINT8 EndOfPostMessage;
-/** Offset 0x1BF7 - D0I3 Setting for HECI Disable
+/** Offset 0x1C2B - D0I3 Setting for HECI Disable
Test, 0: disable, 1: enable, Setting this option disables setting D0I3 bit for all
HECI devices
$EN_DIS
**/
UINT8 DisableD0I3SettingForHeci;
-/** Offset 0x1BF8 - Mctp Broadcast Cycle
+/** Offset 0x1C2C - Mctp Broadcast Cycle
Test, Determine if MCTP Broadcast is enabled <b>0: Disable</b>; 1: Enable.
$EN_DIS
**/
UINT8 MctpBroadcastCycle;
-/** Offset 0x1BF9 - ME Unconfig on RTC clear
+/** Offset 0x1C2D - ME Unconfig on RTC clear
0: Disable ME Unconfig On Rtc Clear. <b>1: Enable ME Unconfig On Rtc Clear</b>.
2: Cmos is clear, status unkonwn. 3: Reserved
0: Disable ME Unconfig On Rtc Clear, 1: Enable ME Unconfig On Rtc Clear, 2: Cmos
@@ -2986,159 +2980,159 @@ typedef struct {
**/
UINT8 MeUnconfigOnRtcClear;
-/** Offset 0x1BFA - Enforce Enhanced Debug Mode
+/** Offset 0x1C2E - Enforce Enhanced Debug Mode
Determine if ME should enter Enhanced Debug Mode. <b>0: disable</b>, 1: enable
$EN_DIS
**/
UINT8 EnforceEDebugMode;
-/** Offset 0x1BFB - Reserved
+/** Offset 0x1C2F - Reserved
**/
UINT8 Reserved65[17];
-/** Offset 0x1C0C - Enable LOCKDOWN SMI
+/** Offset 0x1C40 - Enable LOCKDOWN SMI
Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit.
$EN_DIS
**/
UINT8 PchLockDownGlobalSmi;
-/** Offset 0x1C0D - Enable LOCKDOWN BIOS Interface
+/** Offset 0x1C41 - Enable LOCKDOWN BIOS Interface
Enable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register.
$EN_DIS
**/
UINT8 PchLockDownBiosInterface;
-/** Offset 0x1C0E - Unlock all GPIO pads
+/** Offset 0x1C42 - Unlock all GPIO pads
Force all GPIO pads to be unlocked for debug purpose.
$EN_DIS
**/
UINT8 PchUnlockGpioPads;
-/** Offset 0x1C0F - PCH Unlock SideBand access
+/** Offset 0x1C43 - PCH Unlock SideBand access
The SideBand PortID mask for certain end point (e.g. PSFx) will be locked before
3rd party code execution. 0: Lock SideBand access; 1: Unlock SideBand access.
$EN_DIS
**/
UINT8 PchSbAccessUnlock;
-/** Offset 0x1C10 - Reserved
+/** Offset 0x1C44 - Reserved
**/
UINT8 Reserved66[2];
-/** Offset 0x1C12 - PCIE RP Ltr Max Snoop Latency
+/** Offset 0x1C46 - PCIE RP Ltr Max Snoop Latency
Latency Tolerance Reporting, Max Snoop Latency.
**/
UINT16 PcieRpLtrMaxSnoopLatency[29];
-/** Offset 0x1C4C - PCIE RP Ltr Max No Snoop Latency
+/** Offset 0x1C80 - PCIE RP Ltr Max No Snoop Latency
Latency Tolerance Reporting, Max Non-Snoop Latency.
**/
UINT16 PcieRpLtrMaxNoSnoopLatency[29];
-/** Offset 0x1C86 - PCIE RP Snoop Latency Override Mode
+/** Offset 0x1CBA - PCIE RP Snoop Latency Override Mode
Latency Tolerance Reporting, Snoop Latency Override Mode.
**/
UINT8 PcieRpSnoopLatencyOverrideMode[29];
-/** Offset 0x1CA3 - PCIE RP Snoop Latency Override Multiplier
+/** Offset 0x1CD7 - PCIE RP Snoop Latency Override Multiplier
Latency Tolerance Reporting, Snoop Latency Override Multiplier.
**/
UINT8 PcieRpSnoopLatencyOverrideMultiplier[29];
-/** Offset 0x1CC0 - PCIE RP Snoop Latency Override Value
+/** Offset 0x1CF4 - PCIE RP Snoop Latency Override Value
Latency Tolerance Reporting, Snoop Latency Override Value.
**/
UINT16 PcieRpSnoopLatencyOverrideValue[29];
-/** Offset 0x1CFA - PCIE RP Non Snoop Latency Override Mode
+/** Offset 0x1D2E - PCIE RP Non Snoop Latency Override Mode
Latency Tolerance Reporting, Non-Snoop Latency Override Mode.
**/
UINT8 PcieRpNonSnoopLatencyOverrideMode[29];
-/** Offset 0x1D17 - PCIE RP Non Snoop Latency Override Multiplier
+/** Offset 0x1D4B - PCIE RP Non Snoop Latency Override Multiplier
Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier.
**/
UINT8 PcieRpNonSnoopLatencyOverrideMultiplier[29];
-/** Offset 0x1D34 - PCIE RP Non Snoop Latency Override Value
+/** Offset 0x1D68 - PCIE RP Non Snoop Latency Override Value
Latency Tolerance Reporting, Non-Snoop Latency Override Value.
**/
UINT16 PcieRpNonSnoopLatencyOverrideValue[29];
-/** Offset 0x1D6E - PCIE RP Slot Power Limit Scale
+/** Offset 0x1DA2 - PCIE RP Slot Power Limit Scale
Specifies scale used for slot power limit value. Leave as 0 to set to default.
**/
UINT8 PcieRpSlotPowerLimitScale[29];
-/** Offset 0x1D8B - Reserved
+/** Offset 0x1DBF - Reserved
**/
UINT8 Reserved67;
-/** Offset 0x1D8C - PCIE RP Slot Power Limit Value
+/** Offset 0x1DC0 - PCIE RP Slot Power Limit Value
Specifies upper limit on power supplie by slot. Leave as 0 to set to default.
**/
UINT16 PcieRpSlotPowerLimitValue[29];
-/** Offset 0x1DC6 - PCIE RP Enable Port8xh Decode
+/** Offset 0x1DFA - PCIE RP Enable Port8xh Decode
This member describes whether PCIE root port Port 8xh Decode is enabled. 0: Disable;
1: Enable.
$EN_DIS
**/
UINT8 PcieEnablePort8xhDecode;
-/** Offset 0x1DC7 - PCIE Port8xh Decode Port Index
+/** Offset 0x1DFB - PCIE Port8xh Decode Port Index
The Index of PCIe Port that is selected for Port8xh Decode (0 Based).
**/
UINT8 PchPciePort8xhDecodePortIndex;
-/** Offset 0x1DC8 - PCH Energy Reporting
+/** Offset 0x1DFC - PCH Energy Reporting
Disable/Enable PCH to CPU energy report feature.
$EN_DIS
**/
UINT8 PchPmDisableEnergyReport;
-/** Offset 0x1DC9 - PCH Sata Test Mode
+/** Offset 0x1DFD - PCH Sata Test Mode
Allow entrance to the PCH SATA test modes.
$EN_DIS
**/
UINT8 SataTestMode;
-/** Offset 0x1DCA - PCH USB OverCurrent mapping lock enable
+/** Offset 0x1DFE - PCH USB OverCurrent mapping lock enable
If this policy option is enabled then BIOS will program OCCFDONE bit in xHCI meaning
that OC mapping data will be consumed by xHCI and OC mapping registers will be locked.
$EN_DIS
**/
UINT8 PchXhciOcLock;
-/** Offset 0x1DCB - Low Power Mode Enable/Disable config mask
+/** Offset 0x1DFF - Low Power Mode Enable/Disable config mask
Configure if respective S0i2/3 sub-states are to be supported. Each bit corresponds
to one sub-state (LPMx - BITx): LPM0-s0i2.0, LPM1-s0i2.1, LPM2-s0i2.2, LPM3-s0i3.0,
LPM4-s0i3.1, LPM5-s0i3.2, LPM6-s0i3.3, LPM7-s0i3.4.
**/
UINT8 PmcLpmS0ixSubStateEnableMask;
-/** Offset 0x1DCC - Reserved
+/** Offset 0x1E00 - Reserved
**/
- UINT8 Reserved68[4];
+ UINT8 Reserved68[5];
-/** Offset 0x1DD0 - PMC C10 dynamic threshold dajustment enable
+/** Offset 0x1E05 - PMC C10 dynamic threshold dajustment enable
Set if you want to enable PMC C10 dynamic threshold adjustment. Only works on supported SKUs
$EN_DIS
**/
UINT8 PmcC10DynamicThresholdAdjustment;
-/** Offset 0x1DD1 - Reserved
+/** Offset 0x1E06 - Reserved
**/
- UINT8 Reserved69[35];
+ UINT8 Reserved69[34];
-/** Offset 0x1DF4 - FspEventHandler
+/** Offset 0x1E28 - FspEventHandler
<b>Optional</b> pointer to the boot loader's implementation of FSP_EVENT_HANDLER.
**/
UINT32 FspEventHandler;
-/** Offset 0x1DF8 - Reserved
+/** Offset 0x1E2C - Reserved
**/
- UINT8 Reserved70[16];
+ UINT8 Reserved70[20];
} FSP_S_CONFIG;
/** Fsp S UPD Configuration
@@ -3157,11 +3151,11 @@ typedef struct {
**/
FSP_S_CONFIG FspsConfig;
-/** Offset 0x1E08
+/** Offset 0x1E40
**/
UINT8 Rsvd600[6];
-/** Offset 0x1E0E
+/** Offset 0x1E46
**/
UINT16 UpdTerminator;
} FSPS_UPD;
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-15 05:08:30 +0000