diff options
| -rw-r--r-- | src/mainboard/intel/amenia/devicetree.cb | 9 | ||||
| -rw-r--r-- | src/mainboard/intel/amenia/ec.h | 8 | ||||
| -rw-r--r-- | src/mainboard/intel/amenia/gpio.h | 2 |
3 files changed, 15 insertions, 4 deletions
diff --git a/src/mainboard/intel/amenia/devicetree.cb b/src/mainboard/intel/amenia/devicetree.cb index 7045f59b5d..3b25b2b00a 100644 --- a/src/mainboard/intel/amenia/devicetree.cb +++ b/src/mainboard/intel/amenia/devicetree.cb @@ -18,6 +18,15 @@ chip soc/intel/apollolake # LPSS S0ix Enable register "lpss_s0ix_enable" = "1" + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route, i.e., if this route changes then the affected GPE + # offset bits also need to be changed. This sets the PMC register + # GPE_CFG fields. + register "gpe0_dw1" = "PMC_GPE_N_31_0" + register "gpe0_dw2" = "PMC_GPE_N_63_32" + register "gpe0_dw3" = "PMC_GPE_SW_31_0" + device domain 0 on device pci 00.0 on end # - Host Bridge device pci 00.1 on end # - DPTF diff --git a/src/mainboard/intel/amenia/ec.h b/src/mainboard/intel/amenia/ec.h index 91890fd63e..ba3962af95 100644 --- a/src/mainboard/intel/amenia/ec.h +++ b/src/mainboard/intel/amenia/ec.h @@ -20,9 +20,11 @@ #include <ec/google/chromeec/ec_commands.h> -/* This is the GPE status bit. - TODO: Fix this to proper bit matching GPE routing table */ -#define EC_SCI_GPI 15 +/* + * GPIO_11 for SCI is routed to GPE0_DW1 and maps to group GPIO_GPE_N_31_0 + * which is North community + */ +#define EC_SCI_GPI GPE0_DW1_11 #define MAINBOARD_EC_SCI_EVENTS \ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ diff --git a/src/mainboard/intel/amenia/gpio.h b/src/mainboard/intel/amenia/gpio.h index 87d6190672..a39cca3335 100644 --- a/src/mainboard/intel/amenia/gpio.h +++ b/src/mainboard/intel/amenia/gpio.h @@ -239,7 +239,7 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPIO_8, NATIVE, DEEP, NF1), PAD_CFG_GPI(GPIO_9, UP_20K, DEEP), /* SPI_TPM_IRQ_N */ PAD_NC(GPIO_10, DN_20K), /* RSVD for MIPI (unused) */ - PAD_CFG_GPI_SCI(GPIO_11, UP_20K, DEEP, LEVEL, NONE), + PAD_CFG_GPI_SCI(GPIO_11, UP_20K, DEEP, EDGE_SINGLE, INVERT), /* SOC_WAKE_SCI_N */ PAD_NC(GPIO_12, DN_20K), PAD_NC(GPIO_13, DN_20K), |