diff options
11 files changed, 11 insertions, 11 deletions
diff --git a/src/mainboard/google/puff/variants/ambassador/overridetree.cb b/src/mainboard/google/puff/variants/ambassador/overridetree.cb index 8b6a9ae1b1..93e1c0461c 100644 --- a/src/mainboard/google/puff/variants/ambassador/overridetree.cb +++ b/src/mainboard/google/puff/variants/ambassador/overridetree.cb @@ -396,7 +396,7 @@ chip soc/intel/cannonlake register "wake" = "GPE0_DW1_07" # GPP_C7 register "device_index" = "0" register "enable_aspm_l1_2" = "1" - device pci 00.0 on end + device generic 0 on end end register "PcieRpSlotImplemented[6]" = "1" end # RTL8111H Ethernet NIC diff --git a/src/mainboard/google/puff/variants/baseboard/devicetree.cb b/src/mainboard/google/puff/variants/baseboard/devicetree.cb index 6a32bdc142..b7a9674317 100644 --- a/src/mainboard/google/puff/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/puff/variants/baseboard/devicetree.cb @@ -323,7 +323,7 @@ chip soc/intel/cannonlake device pci 1d.5 on chip drivers/wifi/generic register "wake" = "GPE0_DW1_01" - device pci 00.0 on end + device generic 0 on end end register "PcieRpSlotImplemented[13]" = "1" end # PCI Express Port 14 (x4) diff --git a/src/mainboard/google/puff/variants/duffy/overridetree.cb b/src/mainboard/google/puff/variants/duffy/overridetree.cb index b1c50a2701..4681e5e489 100644 --- a/src/mainboard/google/puff/variants/duffy/overridetree.cb +++ b/src/mainboard/google/puff/variants/duffy/overridetree.cb @@ -455,7 +455,7 @@ chip soc/intel/cannonlake register "wake" = "GPE0_DW1_07" # GPP_C7 register "device_index" = "0" register "enable_aspm_l1_2" = "1" - device pci 00.0 on end + device generic 0 on end end register "PcieRpSlotImplemented[6]" = "1" end # RTL8111H Ethernet NIC diff --git a/src/mainboard/google/puff/variants/faffy/overridetree.cb b/src/mainboard/google/puff/variants/faffy/overridetree.cb index 83f0c166e8..91d7482ae2 100644 --- a/src/mainboard/google/puff/variants/faffy/overridetree.cb +++ b/src/mainboard/google/puff/variants/faffy/overridetree.cb @@ -429,7 +429,7 @@ chip soc/intel/cannonlake register "wake" = "GPE0_DW1_07" # GPP_C7 register "device_index" = "0" register "enable_aspm_l1_2" = "1" - device pci 00.0 on end + device generic 0 on end end register "PcieRpSlotImplemented[6]" = "1" end # RTL8111H Ethernet NIC diff --git a/src/mainboard/google/puff/variants/genesis/overridetree.cb b/src/mainboard/google/puff/variants/genesis/overridetree.cb index 6458f9f3f5..da7648725e 100644 --- a/src/mainboard/google/puff/variants/genesis/overridetree.cb +++ b/src/mainboard/google/puff/variants/genesis/overridetree.cb @@ -426,7 +426,7 @@ chip soc/intel/cannonlake register "wake" = "GPE0_DW1_07" # GPP_C7 register "device_index" = "0" register "enable_aspm_l1_2" = "1" - device pci 00.0 on end + device generic 0 on end end end device pci 1c.7 on # PCI Root Port 8 (WLAN) diff --git a/src/mainboard/google/puff/variants/kaisa/overridetree.cb b/src/mainboard/google/puff/variants/kaisa/overridetree.cb index 6a2dd7b3af..19f0823901 100644 --- a/src/mainboard/google/puff/variants/kaisa/overridetree.cb +++ b/src/mainboard/google/puff/variants/kaisa/overridetree.cb @@ -455,7 +455,7 @@ chip soc/intel/cannonlake register "wake" = "GPE0_DW1_07" # GPP_C7 register "device_index" = "0" register "enable_aspm_l1_2" = "1" - device pci 00.0 on end + device generic 0 on end end register "PcieRpSlotImplemented[6]" = "1" end # RTL8111H Ethernet NIC diff --git a/src/mainboard/google/puff/variants/moonbuggy/overridetree.cb b/src/mainboard/google/puff/variants/moonbuggy/overridetree.cb index a89c56dde6..9c6ea6489e 100644 --- a/src/mainboard/google/puff/variants/moonbuggy/overridetree.cb +++ b/src/mainboard/google/puff/variants/moonbuggy/overridetree.cb @@ -428,7 +428,7 @@ chip soc/intel/cannonlake register "wake" = "GPE0_DW1_07" # GPP_C7 register "device_index" = "0" register "enable_aspm_l1_2" = "1" - device pci 00.0 on end + device generic 0 on end end end device pci 1c.7 on # PCI Root Port 8 (WLAN) diff --git a/src/mainboard/google/puff/variants/noibat/overridetree.cb b/src/mainboard/google/puff/variants/noibat/overridetree.cb index 91a193977c..b81c4e489d 100644 --- a/src/mainboard/google/puff/variants/noibat/overridetree.cb +++ b/src/mainboard/google/puff/variants/noibat/overridetree.cb @@ -366,7 +366,7 @@ chip soc/intel/cannonlake register "wake" = "GPE0_DW1_07" # GPP_C7 register "device_index" = "0" register "enable_aspm_l1_2" = "1" - device pci 00.0 on end + device generic 0 on end end register "PcieRpSlotImplemented[6]" = "1" end # RTL8111H Ethernet NIC diff --git a/src/mainboard/google/puff/variants/puff/overridetree.cb b/src/mainboard/google/puff/variants/puff/overridetree.cb index 3cd6a01d21..51832021d8 100644 --- a/src/mainboard/google/puff/variants/puff/overridetree.cb +++ b/src/mainboard/google/puff/variants/puff/overridetree.cb @@ -390,7 +390,7 @@ chip soc/intel/cannonlake register "wake" = "GPE0_DW1_07" # GPP_C7 register "device_index" = "0" register "enable_aspm_l1_2" = "1" - device pci 00.0 on end + device generic 0 on end end register "PcieRpSlotImplemented[6]" = "1" end # RTL8111H Ethernet NIC diff --git a/src/mainboard/google/puff/variants/scout/overridetree.cb b/src/mainboard/google/puff/variants/scout/overridetree.cb index 5462e9b700..4c13e61fa4 100644 --- a/src/mainboard/google/puff/variants/scout/overridetree.cb +++ b/src/mainboard/google/puff/variants/scout/overridetree.cb @@ -406,7 +406,7 @@ chip soc/intel/cannonlake register "wake" = "GPE0_DW1_07" # GPP_C7 register "device_index" = "0" register "enable_aspm_l1_2" = "1" - device pci 00.0 on end + device generic 0 on end end end device pci 1c.7 on # PCI Root Port 8 (WLAN) diff --git a/src/mainboard/google/puff/variants/wyvern/overridetree.cb b/src/mainboard/google/puff/variants/wyvern/overridetree.cb index 60ba0bcf51..de3704c888 100644 --- a/src/mainboard/google/puff/variants/wyvern/overridetree.cb +++ b/src/mainboard/google/puff/variants/wyvern/overridetree.cb @@ -391,7 +391,7 @@ chip soc/intel/cannonlake register "wake" = "GPE0_DW1_07" # GPP_C7 register "device_index" = "0" register "enable_aspm_l1_2" = "1" - device pci 00.0 on end + device generic 0 on end end register "PcieRpSlotImplemented[6]" = "1" end # RTL8111H Ethernet NIC |