diff options
| -rw-r--r-- | src/mainboard/siemens/mc_apl1/variants/mc_apl4/Makefile.inc | 2 | ||||
| -rw-r--r-- | src/mainboard/siemens/mc_apl1/variants/mc_apl4/memory.c | 68 |
2 files changed, 70 insertions, 0 deletions
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/Makefile.inc b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/Makefile.inc index f3c87b2318..caf542fcd2 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/Makefile.inc +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/Makefile.inc @@ -1 +1,3 @@ +romstage-y += memory.c + ramstage-y += mainboard.c diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/memory.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/memory.c new file mode 100644 index 0000000000..9820f1e34e --- /dev/null +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/memory.c @@ -0,0 +1,68 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * Copyright (C) 2017-2018 Siemens AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/variants.h> +#include <commonlib/helpers.h> +#include <soc/meminit.h> + +const struct lpddr4_swizzle_cfg mc_apl4_lpddr4_swizzle = { + /* CH0_DQA[0:31] SoC pins -> U22 LPDDR4 module pins */ + .phys[LP4_PHYS_CH0A] = { + /* DQA[0:7] pins of LPDDR4 module. */ + .dqs[LP4_DQS0] = { 0, 1, 5, 3, 4, 7, 6, 2 }, + /* DQA[8:15] pins of LPDDR4 module. */ + .dqs[LP4_DQS1] = { 11, 15, 14, 9, 8, 12, 13, 10 }, + /* DQB[0:7] pins of LPDDR4 module with offset of 16. */ + .dqs[LP4_DQS2] = { 16, 22, 23, 21, 19, 17, 18, 20 }, + /* DQB[7:15] pins of LPDDR4 module with offset of 16. */ + .dqs[LP4_DQS3] = { 30, 26, 31, 25, 24, 27, 28, 29 }, + }, + .phys[LP4_PHYS_CH0B] = { + /* DQA[0:7] pins of LPDDR4 module. */ + .dqs[LP4_DQS0] = { 7, 3, 2, 1, 4, 0, 6, 5 }, + /* DQA[8:15] pins of LPDDR4 module. */ + .dqs[LP4_DQS1] = { 14, 8, 9, 15, 10, 13, 12, 11 }, + /* DQB[0:7] pins of LPDDR4 module with offset of 16. */ + .dqs[LP4_DQS2] = { 23, 21, 20, 16, 19, 17, 18, 22 }, + /* DQB[7:15] pins of LPDDR4 module with offset of 16. */ + .dqs[LP4_DQS3] = { 24, 25, 26, 28, 29, 31, 30, 27 }, + }, + .phys[LP4_PHYS_CH1A] = { + /* DQA[0:7] pins of LPDDR4 module. */ + .dqs[LP4_DQS0] = { 6, 3, 1, 7, 4, 2, 5, 0 }, + /* DQA[8:15] pins of LPDDR4 module. */ + .dqs[LP4_DQS1] = { 14, 15, 12, 13, 11, 8, 10, 9 }, + /* DQB[0:7] pins of LPDDR4 module with offset of 16. */ + .dqs[LP4_DQS2] = { 16, 22, 17, 18, 20, 21, 23, 19 }, + /* DQB[7:15] pins of LPDDR4 module with offset of 16. */ + .dqs[LP4_DQS3] = { 31, 28, 26, 25, 29, 24, 27, 30 }, + }, + .phys[LP4_PHYS_CH1B] = { + /* DQA[0:7] pins of LPDDR4 module. */ + .dqs[LP4_DQS0] = { 3, 5, 7, 4, 1, 0, 6, 2 }, + /* DQA[8:15] pins of LPDDR4 module. */ + .dqs[LP4_DQS1] = { 14, 13, 10, 11, 15, 9, 8, 12 }, + /* DQB[0:7] pins of LPDDR4 module with offset of 16. */ + .dqs[LP4_DQS2] = { 23, 18, 19, 22, 16, 17, 21, 20 }, + /* DQB[7:15] pins of LPDDR4 module with offset of 16. */ + .dqs[LP4_DQS3] = { 24, 31, 30, 29, 26, 27, 25, 28 }, + }, +}; + +const struct lpddr4_swizzle_cfg *variant_lpddr4_swizzle_config(void) +{ + return &mc_apl4_lpddr4_swizzle; +} |