diff options
| -rw-r--r-- | src/soc/amd/stoneyridge/sb_util.c | 205 |
1 files changed, 121 insertions, 84 deletions
diff --git a/src/soc/amd/stoneyridge/sb_util.c b/src/soc/amd/stoneyridge/sb_util.c index 3005f4101f..b777b1a5c9 100644 --- a/src/soc/amd/stoneyridge/sb_util.c +++ b/src/soc/amd/stoneyridge/sb_util.c @@ -18,118 +18,82 @@ #include <arch/acpi.h> #include <soc/southbridge.h> -void pm_write8(u8 reg, u8 value) -{ - write8((void *)(ACPIMMIO_PMIO_BASE + reg), value); -} - -u8 pm_read8(u8 reg) -{ - return read8((void *)(ACPIMMIO_PMIO_BASE + reg)); -} +/* smbus pci read/write - access registers at 0xfed80000 - currently unused */ -void pm_write16(u8 reg, u16 value) -{ - write16((void *)(ACPIMMIO_PMIO_BASE + reg), value); -} - -u16 pm_read16(u8 reg) -{ - return read16((void *)(ACPIMMIO_PMIO_BASE + reg)); -} - -void misc_write32(u8 reg, u32 value) -{ - write32((void *)(ACPIMMIO_MISC_BASE + reg), value); -} +/* smi read/write - access registers at 0xfed80200 */ -u32 misc_read32(u8 reg) +uint8_t smi_read8(uint8_t offset) { - return read32((void *)(ACPIMMIO_MISC_BASE + reg)); + return read8((void *)(ACPIMMIO_SMI_BASE + offset)); } -void pm_write32(u8 reg, u32 value) +uint16_t smi_read16(uint8_t offset) { - write32((void *)(ACPIMMIO_PMIO_BASE + reg), value); + return read16((void *)(ACPIMMIO_SMI_BASE + offset)); } -u32 pm_read32(u8 reg) +uint32_t smi_read32(uint8_t offset) { - return read32((void *)(ACPIMMIO_PMIO_BASE + reg)); + return read32((void *)(ACPIMMIO_SMI_BASE + offset)); } -u8 acpi_read8(u8 reg) +void smi_write8(uint8_t offset, uint8_t value) { - return read8((void *)(ACPIMMIO_ACPI_BASE + reg)); + write8((void *)(ACPIMMIO_SMI_BASE + offset), value); } -u16 acpi_read16(u8 reg) +void smi_write16(uint8_t offset, uint16_t value) { - return read16((void *)(ACPIMMIO_ACPI_BASE + reg)); + write16((void *)(ACPIMMIO_SMI_BASE + offset), value); } -u32 acpi_read32(u8 reg) +void smi_write32(uint8_t offset, uint32_t value) { - return read32((void *)(ACPIMMIO_ACPI_BASE + reg)); + write32((void *)(ACPIMMIO_SMI_BASE + offset), value); } -void acpi_write8(u8 reg, u8 value) -{ - write8((void *)(ACPIMMIO_ACPI_BASE + reg), value); -} +/* pm read/write - access registers at 0xfed80300 */ -void acpi_write16(u8 reg, u16 value) +u8 pm_read8(u8 reg) { - write16((void *)(ACPIMMIO_ACPI_BASE + reg), value); + return read8((void *)(ACPIMMIO_PMIO_BASE + reg)); } -void acpi_write32(u8 reg, u32 value) +u16 pm_read16(u8 reg) { - write32((void *)(ACPIMMIO_ACPI_BASE + reg), value); + return read16((void *)(ACPIMMIO_PMIO_BASE + reg)); } -void smi_write32(uint8_t offset, uint32_t value) +u32 pm_read32(u8 reg) { - write32((void *)(ACPIMMIO_SMI_BASE + offset), value); + return read32((void *)(ACPIMMIO_PMIO_BASE + reg)); } -uint32_t smi_read32(uint8_t offset) +void pm_write8(u8 reg, u8 value) { - return read32((void *)(ACPIMMIO_SMI_BASE + offset)); + write8((void *)(ACPIMMIO_PMIO_BASE + reg), value); } -uint16_t smi_read16(uint8_t offset) +void pm_write16(u8 reg, u16 value) { - return read16((void *)(ACPIMMIO_SMI_BASE + offset)); + write16((void *)(ACPIMMIO_PMIO_BASE + reg), value); } -void smi_write16(uint8_t offset, uint16_t value) +void pm_write32(u8 reg, u32 value) { - write16((void *)(ACPIMMIO_SMI_BASE + offset), value); + write32((void *)(ACPIMMIO_PMIO_BASE + reg), value); } -uint8_t smi_read8(uint8_t offset) -{ - return read8((void *)(ACPIMMIO_SMI_BASE + offset)); -} +/* pm2 read/write - access registers at 0xfed80400 - currently unused */ -void smi_write8(uint8_t offset, uint8_t value) -{ - write8((void *)(ACPIMMIO_SMI_BASE + offset), value); -} +/* biosram read/write - access registers at 0xfed80500 */ uint8_t biosram_read8(uint8_t offset) { return read8((void *)(ACPIMMIO_BIOSRAM_BASE + offset)); } -void biosram_write8(uint8_t offset, uint8_t value) -{ - write8((void *)(ACPIMMIO_BIOSRAM_BASE + offset), value); -} - -/* BiosRam may only be accessed a byte at a time */ -uint16_t biosram_read16(uint8_t offset) +uint16_t biosram_read16(uint8_t offset) /* Must be 1 byte at a time */ { int i; uint16_t value = 0; @@ -144,6 +108,11 @@ uint32_t biosram_read32(uint8_t offset) return value | biosram_read16(offset); } +void biosram_write8(uint8_t offset, uint8_t value) +{ + write8((void *)(ACPIMMIO_BIOSRAM_BASE + offset), value); +} + void biosram_write16(uint8_t offset, uint16_t value) { int i; @@ -162,39 +131,88 @@ void biosram_write32(uint8_t offset, uint32_t value) } } -uint16_t pm_acpi_pm_cnt_blk(void) +/* cmosram read/write - access registers at 0xfed80600 - currently unused */ + +/* cmos read/write - access registers at 0xfed80700 - currently unused */ + +/* acpi read/write - access registers at 0xfed80800 */ + +u8 acpi_read8(u8 reg) { - return pm_read16(PM1_CNT_BLK); + return read8((void *)(ACPIMMIO_ACPI_BASE + reg)); } -uint16_t pm_acpi_pm_evt_blk(void) +u16 acpi_read16(u8 reg) { - return pm_read16(PM_EVT_BLK); + return read16((void *)(ACPIMMIO_ACPI_BASE + reg)); } -void xhci_pm_write8(uint8_t reg, uint8_t value) +u32 acpi_read32(u8 reg) { - write8((void *)(ACPIMMIO_XHCIPM_BASE + reg), value); + return read32((void *)(ACPIMMIO_ACPI_BASE + reg)); } -uint8_t xhci_pm_read8(uint8_t reg) +void acpi_write8(u8 reg, u8 value) { - return read8((void *)(ACPIMMIO_XHCIPM_BASE + reg)); + write8((void *)(ACPIMMIO_ACPI_BASE + reg), value); } -void xhci_pm_write16(uint8_t reg, uint16_t value) +void acpi_write16(u8 reg, u16 value) { - write16((void *)(ACPIMMIO_XHCIPM_BASE + reg), value); + write16((void *)(ACPIMMIO_ACPI_BASE + reg), value); } -uint16_t xhci_pm_read16(uint8_t reg) +void acpi_write32(u8 reg, u32 value) { - return read16((void *)(ACPIMMIO_XHCIPM_BASE + reg)); + write32((void *)(ACPIMMIO_ACPI_BASE + reg), value); } -void xhci_pm_write32(uint8_t reg, uint32_t value) +/* smbus read/write - access registers at 0xfed80a00 and ASF at 0xfed80900 */ + +void smbus_write8(uint32_t mmio, uint8_t reg, uint8_t value) { - write32((void *)(ACPIMMIO_XHCIPM_BASE + reg), value); + write8((void *)(mmio + reg), value); +} + +uint8_t smbus_read8(uint32_t mmio, uint8_t reg) +{ + return read8((void *)(mmio + reg)); +} + +/* wdt read/write - access registers at 0xfed80b00 - not currently used */ + +/* hpet read/write - access registers at 0xfed80c00 - not currently used */ + +/* iomux read/write - access registers at 0xfed80d00 - not currently used */ + +/* misc read/write - access registers at 0xfed80e00 */ + +u32 misc_read32(u8 reg) +{ + return read32((void *)(ACPIMMIO_MISC_BASE + reg)); +} + +void misc_write32(u8 reg, u32 value) +{ + write32((void *)(ACPIMMIO_MISC_BASE + reg), value); +} + +/* dpvga read/write - access registers at 0xfed81400 - not currently used */ + +/* gpio bk 0 read/write - access registers at 0xfed81500 - not currently used */ +/* gpio bk 1 read/write - access registers at 0xfed81600 - not currently used */ +/* gpio bk 2 read/write - access registers at 0xfed81700 - not currently used */ + +/* xhci_pm read/write - access registers at 0xfed81c00 */ + +uint8_t xhci_pm_read8(uint8_t reg) +{ + return read8((void *)(ACPIMMIO_XHCIPM_BASE + reg)); +} + +uint16_t xhci_pm_read16(uint8_t reg) +{ + return read16((void *)(ACPIMMIO_XHCIPM_BASE + reg)); } uint32_t xhci_pm_read32(uint8_t reg) @@ -202,14 +220,33 @@ uint32_t xhci_pm_read32(uint8_t reg) return read32((void *)(ACPIMMIO_XHCIPM_BASE + reg)); } -void smbus_write8(uint32_t mmio, uint8_t reg, uint8_t value) +void xhci_pm_write8(uint8_t reg, uint8_t value) { - write8((void *)(mmio + reg), value); + write8((void *)(ACPIMMIO_XHCIPM_BASE + reg), value); } -uint8_t smbus_read8(uint32_t mmio, uint8_t reg) +void xhci_pm_write16(uint8_t reg, uint16_t value) { - return read8((void *)(mmio + reg)); + write16((void *)(ACPIMMIO_XHCIPM_BASE + reg), value); +} + +void xhci_pm_write32(uint8_t reg, uint32_t value) +{ + write32((void *)(ACPIMMIO_XHCIPM_BASE + reg), value); +} + +/* acdc_tmr read/write - access registers at 0xfed81d00 */ + +/* aoac read/write - access registers at 0xfed81e00 - not currently used */ + +uint16_t pm_acpi_pm_cnt_blk(void) +{ + return pm_read16(PM1_CNT_BLK); +} + +uint16_t pm_acpi_pm_evt_blk(void) +{ + return pm_read16(PM_EVT_BLK); } int acpi_get_sleep_type(void) |