diff options
| -rw-r--r-- | src/cpu/allwinner/a10/uart.c | 5 | ||||
| -rw-r--r-- | src/cpu/allwinner/a10/uart_console.c | 22 |
2 files changed, 9 insertions, 18 deletions
diff --git a/src/cpu/allwinner/a10/uart.c b/src/cpu/allwinner/a10/uart.c index 97ac302ddc..990026be26 100644 --- a/src/cpu/allwinner/a10/uart.c +++ b/src/cpu/allwinner/a10/uart.c @@ -7,6 +7,7 @@ #include "uart.h" #include <arch/io.h> +#include <uart.h> #include <uart8250.h> /** @@ -19,11 +20,11 @@ void a10_uart_configure(void *uart_base, u32 baud_rate, u8 data_bits, u16 div; struct a10_uart *uart = uart_base; + div = (u16) uart_baudrate_divisor(baud_rate, + uart_platform_refclk(), 16); /* Enable access to Divisor Latch register */ write32(UART_LCR_DLAB, &uart->lcr); /* Set baudrate */ - /* FIXME: We assume clock is 24MHz, which may not be the case */ - div = 24000000 / 16 / baud_rate; write32((div >> 8) & 0xff, &uart->dlh); write32(div & 0xff, &uart->dll); /* Set line control */ diff --git a/src/cpu/allwinner/a10/uart_console.c b/src/cpu/allwinner/a10/uart_console.c index 58930ddd66..f7bd3c6dc6 100644 --- a/src/cpu/allwinner/a10/uart_console.c +++ b/src/cpu/allwinner/a10/uart_console.c @@ -38,29 +38,19 @@ static void *get_console_uart_base_addr(void) return (void *)A1X_UART0_BASE; } -static u32 get_console_uart_baud(void) +/* FIXME: We assume clock is 24MHz, which may not be the case. */ +unsigned int uart_platform_refclk(void) { - if (CONFIG_CONSOLE_SERIAL_115200) - return 115200; - else if (CONFIG_CONSOLE_SERIAL_57600) - return 57600; - else if (CONFIG_CONSOLE_SERIAL_38400) - return 34800; - else if (CONFIG_CONSOLE_SERIAL_19200) - return 19200; - else if (CONFIG_CONSOLE_SERIAL_9600) - return 9600; - - /* Default to 115200 if selection is invalid */ - return 115200; + return 24000000; } static void a10_uart_init_dev(void) { void *uart_base = get_console_uart_base_addr(); + /* Use default 8N1 encoding */ - a10_uart_configure(uart_base, get_console_uart_baud(), - 8, UART_PARITY_NONE, 1); + a10_uart_configure(uart_base, default_baudrate(), + 8, UART_PARITY_NONE, 1); a10_uart_enable_fifos(uart_base); } |