diff options
| -rw-r--r-- | src/soc/intel/xeon_sp/spr/include/soc/soc_util.h | 5 | ||||
| -rw-r--r-- | src/soc/intel/xeon_sp/spr/romstage.c | 53 |
2 files changed, 58 insertions, 0 deletions
diff --git a/src/soc/intel/xeon_sp/spr/include/soc/soc_util.h b/src/soc/intel/xeon_sp/spr/include/soc/soc_util.h index 97938ead91..997cdb4870 100644 --- a/src/soc/intel/xeon_sp/spr/include/soc/soc_util.h +++ b/src/soc/intel/xeon_sp/spr/include/soc/soc_util.h @@ -25,6 +25,9 @@ #endif #endif +/* Equals to MAX_IIO_PORTS_PER_SOCKET - 2 * 8, because IOU5 and IOU6 are not used per socket. */ +#define IIO_PORT_SETTINGS (1 + 5 * 8) + const struct SystemMemoryMapHob *get_system_memory_map(void); const struct SystemMemoryMapElement *get_system_memory_map_elment(uint8_t *num); @@ -45,5 +48,7 @@ const EWL_PRIVATE_DATA *get_ewl_hob(void); uint32_t get_ubox_busno(uint32_t socket, uint8_t offset); uint32_t get_socket_ubox_busno(uint32_t socket); void soc_set_mrc_cold_boot_flag(bool cold_boot_required); +void soc_config_iio(FSPM_UPD *mupd, const UPD_IIO_PCIE_PORT_CONFIG_ENTRY + mb_iio_table[CONFIG_MAX_SOCKET][IIO_PORT_SETTINGS], const UINT8 mb_iio_bifur[CONFIG_MAX_SOCKET][5]); #endif /* _SOC_UTIL_H_ */ diff --git a/src/soc/intel/xeon_sp/spr/romstage.c b/src/soc/intel/xeon_sp/spr/romstage.c index 0443df1f60..57f12c5d4d 100644 --- a/src/soc/intel/xeon_sp/spr/romstage.c +++ b/src/soc/intel/xeon_sp/spr/romstage.c @@ -119,6 +119,7 @@ static void initialize_iio_upd(FSPM_UPD *mupd) unsigned int port, socket; mupd->FspmConfig.IioPcieConfigTablePtr = (UINT32)spr_iio_bifur_table; + /* MAX_SOCKET is the maximal number defined by FSP, currently is 4. */ mupd->FspmConfig.IioPcieConfigTableNumber = MAX_SOCKET; UPD_IIO_PCIE_PORT_CONFIG *PciePortConfig = (UPD_IIO_PCIE_PORT_CONFIG *)spr_iio_bifur_table; @@ -141,6 +142,58 @@ static void initialize_iio_upd(FSPM_UPD *mupd) DeEmphasisConfig[port] = 0x1; } +void soc_config_iio(FSPM_UPD *mupd, const UPD_IIO_PCIE_PORT_CONFIG_ENTRY + mb_iio_table[CONFIG_MAX_SOCKET][IIO_PORT_SETTINGS], const UINT8 mb_iio_bifur[CONFIG_MAX_SOCKET][5]) +{ + UPD_IIO_PCIE_PORT_CONFIG *PciePortConfig; + int port, socket; + + PciePortConfig = + (UPD_IIO_PCIE_PORT_CONFIG *)(UINTN)mupd->FspmConfig.IioPcieConfigTablePtr; + mupd->FspmConfig.IioPcieConfigTableNumber = CONFIG_MAX_SOCKET; /* Set by mainboard */ + + for (socket = 0; socket < CONFIG_MAX_SOCKET; socket++) { + + /* Configures DMI, IOU0 ~ IOU4 */ + for (port = 0; port < IIO_PORT_SETTINGS; port++) { + const UPD_IIO_PCIE_PORT_CONFIG_ENTRY *port_cfg = + &mb_iio_table[socket][port]; + PciePortConfig[socket].SLOTIMP[port] = port_cfg->SLOTIMP; + PciePortConfig[socket].SLOTPSP[port] = port_cfg->SLOTPSP; + PciePortConfig[socket].SLOTHPCAP[port] = port_cfg->SLOTHPCAP; + PciePortConfig[socket].SLOTHPSUP[port] = port_cfg->SLOTHPSUP; + PciePortConfig[socket].SLOTSPLS[port] = port_cfg->SLOTSPLS; + PciePortConfig[socket].SLOTSPLV[port] = port_cfg->SLOTSPLV; + PciePortConfig[socket].VppAddress[port] = port_cfg->VppAddress; + PciePortConfig[socket].SLOTPIP[port] = port_cfg->SLOTPIP; + PciePortConfig[socket].SLOTAIP[port] = port_cfg->SLOTAIP; + PciePortConfig[socket].SLOTMRLSP[port] = port_cfg->SLOTMRLSP; + PciePortConfig[socket].SLOTPCP[port] = port_cfg->SLOTPCP; + PciePortConfig[socket].SLOTABP[port] = port_cfg->SLOTABP; + PciePortConfig[socket].VppEnabled[port] = port_cfg->VppEnabled; + PciePortConfig[socket].VppPort[port] = port_cfg->VppPort; + PciePortConfig[socket].MuxAddress[port] = port_cfg->MuxAddress; + PciePortConfig[socket].PciePortEnable[port] = port_cfg->PciePortEnable; + PciePortConfig[socket].PEXPHIDE[port] = port_cfg->PEXPHIDE; + PciePortConfig[socket].PcieHotPlugOnPort[port] = port_cfg->PcieHotPlugOnPort; + PciePortConfig[socket].PcieMaxPayload[port] = port_cfg->PcieMaxPayload; + PciePortConfig[socket].PciePortLinkSpeed[port] = port_cfg->PciePortLinkSpeed; + PciePortConfig[socket].DfxDnTxPresetGen3[port] = port_cfg->DfxDnTxPresetGen3; + PciePortConfig[socket].HidePEXPMenu[port] = port_cfg->HidePEXPMenu; + } + + /* Socket IOU5 ~ IOU6 are not used, set PEXPHIDE and HidePEXPMenu to 1 */ + for (port = IIO_PORT_SETTINGS; port < MAX_IIO_PORTS_PER_SOCKET; + port++) { + PciePortConfig[socket].PEXPHIDE[port] = 1; + PciePortConfig[socket].HidePEXPMenu[port] = 1; + } + /* Configure IOU0 ~ IOU4 bifurcation */ + for (port = 0; port < 5; port++) + PciePortConfig[socket].ConfigIOU[port] = mb_iio_bifur[socket][port]; + } +} + void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) { FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; |