diff options
| -rw-r--r-- | src/mainboard/google/nyan/romstage.c | 10 | ||||
| -rw-r--r-- | src/mainboard/google/nyan_big/romstage.c | 10 | ||||
| -rw-r--r-- | src/soc/nvidia/tegra124/cbmem.c | 3 | ||||
| -rw-r--r-- | src/soc/nvidia/tegra124/display.c | 2 | ||||
| -rw-r--r-- | src/soc/nvidia/tegra124/sdram.c | 6 | ||||
| -rw-r--r-- | src/soc/nvidia/tegra124/sdram.h | 1 | ||||
| -rw-r--r-- | src/soc/nvidia/tegra124/soc.c | 9 |
7 files changed, 25 insertions, 16 deletions
diff --git a/src/mainboard/google/nyan/romstage.c b/src/mainboard/google/nyan/romstage.c index c3e87fba78..7fb9570669 100644 --- a/src/mainboard/google/nyan/romstage.c +++ b/src/mainboard/google/nyan/romstage.c @@ -71,7 +71,6 @@ static void configure_l2actlr(void) static void __attribute__((noinline)) romstage(void) { - int dram_size_mb; #if CONFIG_COLLECT_TIMESTAMPS uint64_t romstage_start_time = timestamp_get(); #endif @@ -84,15 +83,14 @@ static void __attribute__((noinline)) romstage(void) sdram_init(get_sdram_config()); - /* used for MMU and CBMEM setup */ - dram_size_mb = sdram_size_mb(); - + /* used for MMU and CBMEM setup, in MB */ u32 dram_start = (CONFIG_SYS_SDRAM_BASE >> 20); - u32 dram_end = dram_start + dram_size_mb; /* plus one... */ + u32 dram_end = sdram_max_addressable_mb(); /* plus one... */ + u32 dram_size = dram_end - dram_start; mmu_init(); mmu_config_range(0, dram_start, DCACHE_OFF); - mmu_config_range(dram_start, dram_size_mb, DCACHE_WRITEBACK); + mmu_config_range(dram_start, dram_size, DCACHE_WRITEBACK); mmu_config_range(CONFIG_DRAM_DMA_START >> 20, CONFIG_DRAM_DMA_SIZE >> 20, DCACHE_OFF); mmu_config_range(dram_end, 4096 - dram_end, DCACHE_OFF); diff --git a/src/mainboard/google/nyan_big/romstage.c b/src/mainboard/google/nyan_big/romstage.c index 9c887a82e8..c18138ae90 100644 --- a/src/mainboard/google/nyan_big/romstage.c +++ b/src/mainboard/google/nyan_big/romstage.c @@ -71,7 +71,6 @@ static void configure_l2actlr(void) static void __attribute__((noinline)) romstage(void) { - int dram_size_mb; #if CONFIG_COLLECT_TIMESTAMPS uint64_t romstage_start_time = timestamp_get(); #endif @@ -84,15 +83,14 @@ static void __attribute__((noinline)) romstage(void) sdram_init(get_sdram_config()); - /* used for MMU and CBMEM setup */ - dram_size_mb = sdram_size_mb(); - + /* used for MMU and CBMEM setup, in MB */ u32 dram_start = (CONFIG_SYS_SDRAM_BASE >> 20); - u32 dram_end = dram_start + dram_size_mb; /* plus one... */ + u32 dram_end = sdram_max_addressable_mb(); /* plus one... */ + u32 dram_size = dram_end - dram_start; mmu_init(); mmu_config_range(0, dram_start, DCACHE_OFF); - mmu_config_range(dram_start, dram_size_mb, DCACHE_WRITEBACK); + mmu_config_range(dram_start, dram_size, DCACHE_WRITEBACK); mmu_config_range(CONFIG_DRAM_DMA_START >> 20, CONFIG_DRAM_DMA_SIZE >> 20, DCACHE_OFF); mmu_config_range(dram_end, 4096 - dram_end, DCACHE_OFF); diff --git a/src/soc/nvidia/tegra124/cbmem.c b/src/soc/nvidia/tegra124/cbmem.c index 7f20702e63..9a754a0fea 100644 --- a/src/soc/nvidia/tegra124/cbmem.c +++ b/src/soc/nvidia/tegra124/cbmem.c @@ -23,6 +23,5 @@ void *cbmem_top(void) { - return (void *)(CONFIG_SYS_SDRAM_BASE + - ((sdram_size_mb() - FB_SIZE_MB)<< 20UL)); + return (void *)((sdram_max_addressable_mb() - FB_SIZE_MB) << 20UL); } diff --git a/src/soc/nvidia/tegra124/display.c b/src/soc/nvidia/tegra124/display.c index 00dfbb694d..2fbec50cf8 100644 --- a/src/soc/nvidia/tegra124/display.c +++ b/src/soc/nvidia/tegra124/display.c @@ -228,7 +228,7 @@ static void update_window(struct display_controller *dc, uint32_t fb_base_mb(void) { - return CONFIG_SYS_SDRAM_BASE/MiB + (sdram_size_mb() - FB_SIZE_MB); + return sdram_max_addressable_mb() - FB_SIZE_MB; } /* this is really aimed at the lcd panel. That said, there are two display diff --git a/src/soc/nvidia/tegra124/sdram.c b/src/soc/nvidia/tegra124/sdram.c index dcab810a45..1854e1dbd9 100644 --- a/src/soc/nvidia/tegra124/sdram.c +++ b/src/soc/nvidia/tegra124/sdram.c @@ -22,6 +22,7 @@ #include <delay.h> #include <soc/addressmap.h> #include <soc/clock.h> +#include <stdlib.h> #include "emc.h" #include "mc.h" @@ -639,3 +640,8 @@ int sdram_size_mb(void) printk(BIOS_DEBUG, "%s: Total SDRAM (MB): %u\n", __func__, total_size); return total_size; } + +uintptr_t sdram_max_addressable_mb(void) +{ + return MIN((CONFIG_SYS_SDRAM_BASE/MiB) + sdram_size_mb(), 4096); +} diff --git a/src/soc/nvidia/tegra124/sdram.h b/src/soc/nvidia/tegra124/sdram.h index 66dbaa1ba5..d32ce37770 100644 --- a/src/soc/nvidia/tegra124/sdram.h +++ b/src/soc/nvidia/tegra124/sdram.h @@ -25,6 +25,7 @@ uint32_t sdram_get_ram_code(void); void sdram_init(const struct sdram_params *param); int sdram_size_mb(void); +uintptr_t sdram_max_addressable_mb(void); /* Save params to PMC scratch registers for use by BootROM on LP0 resume. */ void sdram_lp0_save_params(const struct sdram_params *sdram); diff --git a/src/soc/nvidia/tegra124/soc.c b/src/soc/nvidia/tegra124/soc.c index 8ad1aa9730..bc47954790 100644 --- a/src/soc/nvidia/tegra124/soc.c +++ b/src/soc/nvidia/tegra124/soc.c @@ -35,8 +35,15 @@ static void soc_enable(device_t dev) unsigned long fb_size = FB_SIZE_MB; ram_resource(dev, 0, CONFIG_SYS_SDRAM_BASE/KiB, - (sdram_size_mb() - fb_size)*KiB); + (sdram_max_addressable_mb() - fb_size)*KiB - + CONFIG_SYS_SDRAM_BASE/KiB); mmio_resource(dev, 1, lcdbase*KiB, fb_size*KiB); + + u32 sdram_end_mb = sdram_size_mb() + CONFIG_SYS_SDRAM_BASE/MiB; + + if (sdram_end_mb > sdram_max_addressable_mb()) + ram_resource(dev, 2, sdram_max_addressable_mb()*KiB, + (sdram_end_mb - sdram_max_addressable_mb())*KiB); } static void soc_init(device_t dev) |