diff options
| -rw-r--r-- | src/soc/amd/cezanne/romstage.c | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/src/soc/amd/cezanne/romstage.c b/src/soc/amd/cezanne/romstage.c index 52ff0f8e41..509addfa52 100644 --- a/src/soc/amd/cezanne/romstage.c +++ b/src/soc/amd/cezanne/romstage.c @@ -1,7 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <arch/cpu.h> +#include <console/console.h> #include <fsp/api.h> +#include <program_loading.h> void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) { @@ -9,4 +11,15 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) asmlinkage void car_stage_entry(void) { + post_code(0x40); + console_init(); + + post_code(0x41); + + u32 val = cpuid_eax(1); + printk(BIOS_DEBUG, "Family_Model: %08x\n", val); + + fsp_memory_init(false); /* no S3 resume yet */ + + run_ramstage(); } |