diff options
| -rw-r--r-- | src/soc/amd/mendocino/chip.h | 14 | ||||
| -rw-r--r-- | src/soc/amd/mendocino/fsp_m_params.c | 2 |
2 files changed, 16 insertions, 0 deletions
diff --git a/src/soc/amd/mendocino/chip.h b/src/soc/amd/mendocino/chip.h index 42f27cb3a5..f16f5fd4be 100644 --- a/src/soc/amd/mendocino/chip.h +++ b/src/soc/amd/mendocino/chip.h @@ -13,6 +13,16 @@ #include <types.h> #include <vendorcode/amd/fsp/mendocino/FspUsb.h> +/* force USB3 port to gen1, bit0 - controller0 Port0, bit1 - Port1, etc */ +union __packed usb3_force_gen1 { + struct { + uint8_t xhci0_port0:1; + uint8_t xhci1_port0:1; + uint8_t xhci1_port1:1; + } ports; + uint8_t usb3_port_force_gen1_en; +}; + struct soc_amd_mendocino_config { struct soc_amd_common_config common_config; u8 i2c_scl_reset; @@ -163,6 +173,10 @@ struct soc_amd_mendocino_config { /* Set for PCIe optimization w/a and a double confirming on the result of PCIe Signal Integrity is highly recommended. */ uint8_t dxio_tx_vboost_enable; + + /* Force USB3 port to gen1, bit0 - controller0 Port0, bit1 - Port1 */ + union usb3_force_gen1 usb3_port_force_gen1; + }; #endif /* MENDOCINO_CHIP_H */ diff --git a/src/soc/amd/mendocino/fsp_m_params.c b/src/soc/amd/mendocino/fsp_m_params.c index 8533743d51..37d4048a80 100644 --- a/src/soc/amd/mendocino/fsp_m_params.c +++ b/src/soc/amd/mendocino/fsp_m_params.c @@ -174,4 +174,6 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) fsp_fill_pcie_ddi_descriptors(mcfg); fsp_assign_ioapic_upds(mcfg); mb_pre_fspm(mcfg); + + mcfg->fch_usb_3_port_force_gen1 = config->usb3_port_force_gen1.usb3_port_force_gen1_en; } |