diff options
4 files changed, 0 insertions, 670 deletions
diff --git a/src/vendorcode/amd/pi/00670F00/Makefile.inc b/src/vendorcode/amd/pi/00670F00/Makefile.inc index ad3955cc95..61d0480785 100644 --- a/src/vendorcode/amd/pi/00670F00/Makefile.inc +++ b/src/vendorcode/amd/pi/00670F00/Makefile.inc @@ -43,8 +43,6 @@ BINARY_PI_INC += -I$(AGESA_ROOT)/Proc/CPU BINARY_PI_INC += -I$(AGESA_ROOT)/Proc/CPU/Family BINARY_PI_INC += -I$(AGESA_ROOT)/Proc/Fch BINARY_PI_INC += -I$(AGESA_ROOT)/Proc/Fch/Common -BINARY_PI_INC += -I$(AGESA_ROOT)/Proc/Psp/PspBaseLib - AGESA_INC = -I$(obj) AGESA_INC += $(BINARY_PI_INC) @@ -90,8 +88,6 @@ agesa_raw_files += $(wildcard $(AGESA_ROOT)/Lib/*.[cS]) agesa_raw_files += $(wildcard $(AGESA_ROOT)/binaryPI/*.[cS]) -agesa_raw_files += $(wildcard $(AGESA_ROOT)/Proc/Psp/PspBaseLib/*.[cS]) - classes-$(CONFIG_CPU_AMD_AGESA_BINARY_PI) += libagesa ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32),y) diff --git a/src/vendorcode/amd/pi/00670F00/Proc/Psp/PspBaseLib/PspBaseLib.c b/src/vendorcode/amd/pi/00670F00/Proc/Psp/PspBaseLib/PspBaseLib.c deleted file mode 100644 index 392dda6b4c..0000000000 --- a/src/vendorcode/amd/pi/00670F00/Proc/Psp/PspBaseLib/PspBaseLib.c +++ /dev/null @@ -1,315 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * PSP Base Library - * - * Contains interface to the PSP library - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: PSP - * @e \$Revision$ @e \$Date$ - * - */ - /***************************************************************************** - * - * Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Filecode.h" - /* - * Header removed for coreboot. - * #include "Fch.h" - */ -#include "PspBaseLib.h" - -#define FILECODE PROC_PSP_PSPBASELIB_PSPBASELIB_FILECODE -#define PSP_BAR_TMP_BASE 0xFEA00000ul - -#define GET_PCI_BUS(Reg) (((UINT32) Reg >> 16) & 0xFF) -#define GET_PCI_DEV(Reg) (((UINT32) Reg >> 11) & 0x1F) -#define GET_PCI_FUNC(Reg) (((UINT32) Reg >> 8) & 0x7) -#define GET_PCI_OFFSET(Reg) ((UINT32)Reg & 0xFF) - -#define PCI_CONFIG_SMU_INDIRECT_INDEX 0xB8 ///< Gnb Offset index for SMU mbox -#define PCI_CONFIG_SMU_INDIRECT_DATA 0xBC ///< Gnb Offset data for SMU mbox - -#define SMU_CC_PSP_FUSES_STATUS 0xC0018000ul ///< offset in GNB to find PSP fusing -#define SMU_CC_PSP_FUSES_SECURE BIT0 ///< BIT0 -#define SMU_CC_PSP_FUSES_FRA_ENABLE BIT1 ///< BIT1 -#define SMU_CC_PSP_FUSES_PROTO BIT2 ///< BIT2 -#define PLATFORM_SECURE_BOOT_EN BIT4 ///< BIT4 - - -#define PSP_BLANK_PART 0 ///< Blank part -#define PSP_PROTO_PART SMU_CC_PSP_FUSES_PROTO ///< Proto Part -#define PSP_NON_SECURE_PART (SMU_CC_PSP_FUSES_PROTO + SMU_CC_PSP_FUSES_PCPU_DIS) ///< Non Secure Part -#define PSP_SECURE_PART (SMU_CC_PSP_FUSES_PROTO + SMU_CC_PSP_FUSES_SECURE) ///< Secure Part -#define PSP_FRA_MODE (SMU_CC_PSP_FUSES_FRA_ENABLE + SMU_CC_PSP_FUSES_PROTO + SMU_CC_PSP_FUSES_SECURE) ///< FRA Part - -#define PSP_MUTEX_REG0_OFFSET (24 * 4) ///< PSP Mutex0 register offset -#define PSP_MUTEX_REG1_OFFSET (25 * 4) ///< PSP Mutex1 register offset - -#ifndef OFFSET_OF -#define OFFSET_OF(TYPE, Field) ((UINTN) &(((TYPE *)0)->Field)) -#endif - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - - - -UINT32 -PspLibPciReadConfig ( - IN UINT32 Register - ) -{ - UINT32 Value; - PCI_ADDR PciAddr; - - Value = 0; - PciAddr.AddressValue = MAKE_SBDFO (0, GET_PCI_BUS (Register), GET_PCI_DEV (Register), GET_PCI_FUNC (Register), GET_PCI_OFFSET (Register)); - - LibAmdPciRead (AccessWidth32, PciAddr, &Value, NULL); - - return Value; -} - -VOID -PspLibPciWriteConfig ( - IN UINT32 Register, - IN UINT32 Value - ) -{ - PCI_ADDR PciAddr; - PciAddr.AddressValue = MAKE_SBDFO (0, GET_PCI_BUS (Register), GET_PCI_DEV (Register), GET_PCI_FUNC (Register), GET_PCI_OFFSET (Register)); - - LibAmdPciWrite (AccessWidth32, PciAddr, &Value, NULL); - -} - -UINT32 -PspLibPciReadPspConfig ( - IN UINT16 Offset - ) -{ - return (PspLibPciReadConfig ((UINT32) (PSP_PCI_BDA + Offset))); -} - -VOID -PspLibPciWritePspConfig ( - IN UINT16 Offset, - IN UINT32 Value - ) -{ - PspLibPciWriteConfig ((UINT32) (PSP_PCI_BDA + Offset), Value); -} - -/// Structure for Program ID -typedef enum { - CZ_PROGRAM = 0x00, ///< Program ID for CZ - BR_PROGRAM = 0x01, ///< Program ID for BR - ST_PROGRAM = 0x02, ///< Program ID for ST - UNSUPPORTED_PROGRAM = 0xFF, ///< Program ID for unsupported -} PROGRAM_ID; - -static PROGRAM_ID -PspGetProgarmId ( - VOID - ) -{ - CPUID_DATA Cpuid; - - LibAmdCpuidRead (0x00000001, &Cpuid, NULL); - //Stoney CPUID 0x00670F00 or 0x00670F01 - if ((Cpuid.EAX_Reg >> 16) == 0x67) { - return ST_PROGRAM; - } else if ((Cpuid.EAX_Reg >> 16) == 0x66) { - if ((Cpuid.EAX_Reg & 0xF0) == 0x50) { - //Bristol CPUID 0x00660F51 - return BR_PROGRAM; - } else if ((Cpuid.EAX_Reg & 0xF0) == 0x00) { - //Carrizo CPUID 0x00660F00 or 0x00660F01 - return CZ_PROGRAM; - } - } - return UNSUPPORTED_PROGRAM; -} - -BOOLEAN -GetPspDirBase ( - IN OUT UINT32 *Address - ) -{ - UINTN i; - FIRMWARE_ENTRY_TABLE *FirmwareTableBase; - PROGRAM_ID ProgramId; - CONST UINT32 RomSigAddrTable[] = - { - 0xFFFA0000, // --> 512KB base - 0xFFF20000, // --> 1MB base - 0xFFE20000, // --> 2MB base - 0xFFC20000, // --> 4MB base - 0xFF820000, // --> 8MB base - 0xFF020000 // --> 16MB base - }; - - ProgramId = PspGetProgarmId (); - - for (i = 0; i < sizeof (RomSigAddrTable) / sizeof (UINT32); i++) { - FirmwareTableBase = (FIRMWARE_ENTRY_TABLE *) (UINTN) RomSigAddrTable[i]; - // Search flash for unique signature 0x55AA55AA - if (FirmwareTableBase->Signature == FIRMWARE_TABLE_SIGNATURE) { - switch (ProgramId) { - case BR_PROGRAM: - case CZ_PROGRAM: - *Address = FirmwareTableBase->PspDirBase; - break; - case ST_PROGRAM: - *Address = FirmwareTableBase->NewPspDirBase; - break; - default: - *Address = FirmwareTableBase->PspDirBase; - break; - } - return TRUE; - } - } - return (FALSE); -} - -/** - Check if PSP device is present - - @retval BOOLEAN 0: PSP Disabled, 1: PSP Enabled - -**/ -BOOLEAN -CheckPspDevicePresent ( - VOID - ) -{ - UINT32 SecureFuseReg; - PspLibPciWriteConfig ( (UINT32)PCI_CONFIG_SMU_INDIRECT_INDEX, (UINT32)SMU_CC_PSP_FUSES_STATUS); - SecureFuseReg = PspLibPciReadConfig ( (UINT32)PCI_CONFIG_SMU_INDIRECT_DATA); - - if (SecureFuseReg &= SMU_CC_PSP_FUSES_PROTO) { - return (TRUE); - } - return (FALSE); -} - -BOOLEAN -PspBarInitEarly () -{ - UINT32 PspMmioSize; - UINT32 Value32; - - if (PspLibPciReadPspConfig (PSP_PCI_DEVID_REG) == 0xffffffff) { - return (FALSE); - } - - //Check if PSP BAR has been assigned, if not do the PSP BAR initialation - if (PspLibPciReadPspConfig (PSP_PCI_BAR3_REG) == 0) { - /// Get PSP BAR1 Size - PspLibPciWritePspConfig (PSP_PCI_BAR3_REG, 0xFFFFFFFF); - PspMmioSize = PspLibPciReadPspConfig (PSP_PCI_BAR3_REG); - PspMmioSize = ~PspMmioSize + 1; - /// Assign BAR3 Temporary Address - PspLibPciWritePspConfig (PSP_PCI_BAR3_REG, PSP_BAR_TMP_BASE); - PspLibPciWritePspConfig ( PSP_PCI_CMD_REG, 0x06); - - /// Enable GNB redirection to this space @todo use equate & also find proper fix - PspLibPciWriteConfig ( ( (0x18 << 11) + (1 << 8) + 0xBC), ((PSP_BAR_TMP_BASE + PspMmioSize -1) >> 8) & ~0xFF); - PspLibPciWriteConfig ( ( (0x18 << 11) + (1 << 8) + 0xB8), (PSP_BAR_TMP_BASE >> 8) | 3); - /// Enable MsixBarEn, Bar1En, Bar3En - PspLibPciWritePspConfig ( PSP_PCI_EXTRAPCIHDR_REG, 0x34); - /// Capability chain update - Value32 = PspLibPciReadPspConfig (PSP_PCI_MIRRORCTRL1_REG); - Value32 &= ~D8F0x44_PmNxtPtrW_MASK; - Value32 |= 0xA4; - PspLibPciWritePspConfig (PSP_PCI_MIRRORCTRL1_REG, Value32); - } - - return (TRUE); -} - -/** - Return the PspMMIO MMIO location - - @param[in] PspMmio Pointer to Psp MMIO address - - @retval BOOLEAN 0: Error, 1 Success -**/ -BOOLEAN -GetPspBar3Addr ( - IN OUT UINT32 *PspMmio - ) -{ - UINT32 PciReg48; - UINT64 MsrPspAddr; - - if (CheckPspDevicePresent () == FALSE) { - return (FALSE); - } - - PciReg48 = PspLibPciReadPspConfig (PSP_PCI_EXTRAPCIHDR_REG); - if (PciReg48 & BIT12) { - // D8F0x48[12] Bar3Hide - LibAmdMsrRead (PSP_MSR_PRIVATE_BLOCK_BAR, &MsrPspAddr, NULL); - *PspMmio = (UINT32)MsrPspAddr; - } else { - *PspMmio = PspLibPciReadPspConfig (PSP_PCI_BAR3_REG) & 0xFFF00000; - } - - if ((*PspMmio) == 0xffffffff) { - return (FALSE); - } - - return (TRUE); -} diff --git a/src/vendorcode/amd/pi/00670F00/Proc/Psp/PspBaseLib/PspBaseLib.h b/src/vendorcode/amd/pi/00670F00/Proc/Psp/PspBaseLib/PspBaseLib.h deleted file mode 100644 index 4a37f8016f..0000000000 --- a/src/vendorcode/amd/pi/00670F00/Proc/Psp/PspBaseLib/PspBaseLib.h +++ /dev/null @@ -1,238 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * PSP Base Library - * - * Contains interface to the PSP library - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: PSP - * @e \$Revision$ @e \$Date$ - * - */ - /***************************************************************************** - * - * Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - -#include <check_for_wrapper.h> - -#ifndef _PSP_BASE_LIB_H_ -#define _PSP_BASE_LIB_H_ - -#include "AMD.h" -#include "amdlib.h" -#include "PspDirectory.h" - -#define PSP_PCI_SEG 0x00 ///< PSP Seg address -#define PSP_PCI_BUS 0x00 ///< PSP Bus address -#define PSP_PCI_DEV 0x08 ///< PSP Device address -#define PSP_PCI_FN 0x00 ///< PSP Fn address -#define PSP_PCI_BDA ((PSP_PCI_DEV << 11) + (PSP_PCI_FN << 8)) -#define GET_PSP_PCI_ADDR(Offset) MAKE_SBDFO (PSP_PCI_SEG, PSP_PCI_BUS, PSP_PCI_DEV, PSP_PCI_FN, Offset) - -#define PSP_PCI_DEVID_REG 0x00 ///< DevId -#define PSP_PCI_CMD_REG 0x04 ///< CmdReg -#define PSP_PCI_BAR1_REG 0x18 ///< Pci Bar1 -#define PSP_PCI_BAR3_REG 0x20 ///< Pci Bar3 -#define PSP_PCI_MIRRORCTRL1_REG 0x44 ///< PSP Mirror Reg Ctrl 1 -#define PSP_PCI_EXTRAPCIHDR_REG 0x48 ///< Extra PCI Header Ctr -#define PSP_PCI_HTMSICAP_REG 0x5C ///< HT MSI Capability - -#define PSP_MSR_PRIVATE_BLOCK_BAR 0xC00110A2ul ///< PSP Private Block Base Address (PSP_ADDR) - -#define D8F0x44_PmNxtPtrW_MASK 0xff - -#define PSP_MAILBOX_BASE 0x70 ///< Mailbox base offset on PCIe BAR -#define PSP_MAILBOX_STATUS_OFFSET 0x4 ///< Staus Offset - -#define PMIO_INDEX_PORT 0xCD6 ///Pmio index port -#define PMIO_DATA_PORT 0xCD7 ///Pmio data port - -#define PMIO_REG62 0x62 ///PMIOx62 - -//====================================================================================== -// -// Define Mailbox Status field -// -//====================================================================================== -// -/// MBox Status MMIO space -/// -typedef struct { - UINT32 MboxInitialized:1; ///< Target will set this to 1 to indicate it is initialized (for ex. PSP/TPM ready) - UINT32 Error:1; ///< Target in adddtion to Done bit will also set this bit to indicate success/error on last command - UINT32 Terminated:1; ///< Target will set this bit if it aborted the command due to abort request - UINT32 Halt:1; ///< Target will set this error if there is critical error that require reset etc - UINT32 Recovery:1; ///< Target will set this error if some PSP entry point by PSP directory has been corrupted. - UINT32 Reserved:27; ///< Reserved -} MBOX_STATUS; - -// -// Above defined as bitmap -#define MBOX_STATUS_INITIALIZED 0x00000001ul ///< Mailbox Status: Initialized -#define MBOX_STATUS_ERROR 0x00000002ul ///< Mailbox Status: Error -#define MBOX_STATUS_ABORT 0x00000004ul ///< Mailbox Status: Abort -#define MBOX_STATUS_HALT 0x00000008ul ///< Mailbox Status: Halt -#define MBOX_STATUS_RECOVERY 0x00000010ul ///< Mailbox Status: Recovery required - - - -#define PSP_SMM_COMMUNICATION_TYPE_S3SCRIPT 0x1 ///< PspCommunicationType for S3 script - -/// PSP communication structure for S3SCRIPT -typedef struct { - UINT64 PspBar3PciAddr; /// PCI address for PSP BAR3 - UINT32 PspBar3Val; /// PCI register value for PSP BAR3 - UINT64 Pspx48PciAddr; /// PCI address for PSP Register 48 - UINT32 Pspx48Val; /// PCI register value for PSP Register 48 -} PSP_SMM_COMMUNICATION_S3SCRIPT; - -/// Union for PSP_SMM_COMMUNICATE_DATA -typedef union _PSP_SMM_COMMUNICATE_DATA { - PSP_SMM_COMMUNICATION_S3SCRIPT S3Script; ///< S3Script -} PSP_SMM_COMMUNICATE_DATA; - -/// PSP communication header -typedef struct { - UINT32 PspCommunicationType; ///< Type of smm communication buffer - PSP_SMM_COMMUNICATE_DATA Data; ///< Communication buffer -} PSP_SMM_COMMUNICATION_BUFFER; - - -UINT32 -PspLibPciReadConfig ( - IN UINT32 Register - ); - -VOID -PspLibPciWriteConfig ( - IN UINT32 Register, - IN UINT32 Value - ); - -UINT32 -PspLibPciReadPspConfig ( - IN UINT16 Offset - ); - -VOID -PspLibPciWritePspConfig ( - IN UINT16 Offset, - IN UINT32 Value - ); - -BOOLEAN -GetPspDirBase ( - IN OUT UINT32 *Address -); - -BOOLEAN -PSPEntryInfo ( - IN PSP_DIRECTORY_ENTRY_TYPE EntryType, - IN OUT UINT64 *EntryAddress, - IN OUT UINT32 *EntrySize - ); - -BOOLEAN -PspSoftWareFuseInfo ( - IN OUT UINTN *FuseSpiAddress, - IN OUT UINT64 *FuseValue - ); - -VOID -UpdataPspDirCheckSum ( - IN OUT PSP_DIRECTORY *PspDir - ); - -BOOLEAN -CheckPspDevicePresent ( - VOID - ); - -BOOLEAN -CheckPspPlatformSecureEnable ( - VOID - ); - -BOOLEAN -CheckPspRecoveryFlag ( - VOID - ); - -BOOLEAN -GetPspBar1Addr ( - IN OUT UINT32 *PspMmio - ); - -BOOLEAN -GetPspBar3Addr ( - IN OUT UINT32 *PspMmio - ); - -VOID -AcquirePspSmiRegMutex ( - VOID - ); - -VOID -ReleasePspSmiRegMutex ( - VOID - ); - -BOOLEAN -GetPspMboxStatus ( - IN OUT MBOX_STATUS **MboxStatus - ); - - -BOOLEAN -PspBarInitEarly (VOID); - -VOID -PspLibPciIndirectRead ( - IN PCI_ADDR Address, - IN UINT32 IndirectAddress, - IN ACCESS_WIDTH Width, - OUT VOID *Value - ); - -VOID -PspLibPciIndirectWrite ( - IN PCI_ADDR Address, - IN UINT32 IndirectAddress, - IN ACCESS_WIDTH Width, - IN VOID *Value - ); - -BOOLEAN -IsS3Resume (VOID); - - -#endif // _AMD_LIB_H_ diff --git a/src/vendorcode/amd/pi/00670F00/Proc/Psp/PspBaseLib/PspDirectory.h b/src/vendorcode/amd/pi/00670F00/Proc/Psp/PspBaseLib/PspDirectory.h deleted file mode 100644 index f35901e6a6..0000000000 --- a/src/vendorcode/amd/pi/00670F00/Proc/Psp/PspBaseLib/PspDirectory.h +++ /dev/null @@ -1,113 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * PSP directory related functions Prototype definition - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: PSP - * @e \$Revision$ @e \$Date$ - */ - /***************************************************************************** - * - * Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - -#include <check_for_wrapper.h> - -#ifndef _PSP_DIRECTORY_H_ -#define _PSP_DIRECTORY_H_ - - -#define FIRMWARE_TABLE_SIGNATURE 0x55AA55AAul -/// Define the structure OEM signature table -typedef struct _FIRMWARE_ENTRY_TABLE { - UINT32 Signature; ///< Signature should be 0x55AA55AAul - UINT32 ImcRomBase; ///< Base Address for Imc Firmware - UINT32 GecRomBase; ///< Base Address for Gmc Firmware - UINT32 XHCRomBase; ///< Base Address for XHCI Firmware - UINT32 PspDirBase; ///< Base Address for PSP directory - UINT32 NewPspDirBase; ///< Base Address of PSP directory from program start from ST -} FIRMWARE_ENTRY_TABLE; - -/// Define structure for PSP directory -typedef struct { - UINT32 PspCookie; ///< "$PSP" - UINT32 Checksum; ///< 32 bit CRC of header items below and the entire table - UINT32 TotalEntries; ///< Number of PSP Entries - UINT32 Reserved; ///< Unused -} PSP_DIRECTORY_HEADER; - - -/// define various enum type for PSP entry type -enum _PSP_DIRECTORY_ENTRY_TYPE { - AMD_PUBLIC_KEY = 0x00, ///< PSP entry pointer to AMD public key - PSP_FW_BOOT_LOADER = 0x01, ///< PSP entry points to PSP boot loader in SPI space - PSP_FW_TRUSTED_OS = 0x02, ///< PSP entry points to PSP Firmware region in SPI space - PSP_FW_RECOVERY_BOOT_LOADER = 0x03, ///< PSP entry point to PSP recovery region. - PSP_NV_DATA = 0x04, ///< PSP entry points to PSP data region in SPI space - BIOS_PUBLIC_KEY = 0x05, ///< PSP entry points to BIOS public key stored in SPI space - BIOS_RTM_FIRMWARE = 0x06, ///< PSP entry points to BIOS RTM code (PEI volume) in SPI space - BIOS_RTM_SIGNATURE = 0x07, ///< PSP entry points to signed BIOS RTM hash stored in SPI space - SMU_OFFCHIP_FW = 0x08, ///< PSP entry points to SMU image - AMD_SEC_DBG_PUBLIC_KEY = 0x09, ///< PSP entry pointer to Secure Unlock Public key - OEM_PSP_FW_PUBLIC_KEY = 0x0A, ///< PSP entry pointer to an optional public part of the OEM PSP Firmware Signing Key Token - AMD_SOFT_FUSE_CHAIN_01 = 0x0B, ///< PSP entry pointer to 64bit PSP Soft Fuse Chain - PSP_BOOT_TIME_TRUSTLETS = 0x0C, ///< PSP entry points to boot-loaded trustlet binaries - PSP_BOOT_TIME_TRUSTLETS_KEY = 0x0D, ///< PSP entry points to key of the boot-loaded trustlet binaries - PSP_AGESA_RESUME_FW = 0x10, ///< PSP Entry points to PSP Agesa-Resume-Firmware - SMU_OFF_CHIP_FW_2 = 0x12, ///< PSP entry points to secondary SMU image - PSP_S3_NV_DATA = 0x1A, ///< PSP entry pointer to S3 Data Blob - AMD_SCS_BINARY = 0x5F, ///< Software Configuration Settings Data Block -}; - -#define PSP_ENTRY_PROGRAM_ID_0 0 ///< Program identifier 0, used when two programs share the same root key -#define PSP_ENTRY_PROGRAM_ID_1 1 ///< Program identifier 1, used when two programs share the same root key - -#define PSP_ENTRY_CZ_PROGRAM_ID PSP_ENTRY_PROGRAM_ID_0 ///< CZ Program identifier -#define PSP_ENTRY_BR_PROGRAM_ID PSP_ENTRY_PROGRAM_ID_1 ///< BR Program identifier - -typedef UINT32 PSP_DIRECTORY_ENTRY_TYPE; - -/// Structure for PSP Entry -typedef struct { - PSP_DIRECTORY_ENTRY_TYPE Type; ///< Type of PSP entry; 32 bit long - UINT32 Size; ///< Size of PSP Entry in bytes - UINT64 Location; ///< Location of PSP Entry (byte offset from start of SPI-ROM) -} PSP_DIRECTORY_ENTRY; - -/// Structure for PSP directory -typedef struct { - PSP_DIRECTORY_HEADER Header; ///< PSP directory header - PSP_DIRECTORY_ENTRY PspEntry[1]; ///< Array of PSP entries each pointing to a binary in SPI flash - ///< The actual size of this array comes from the - ///< header (PSP_DIRECTORY.Header.TotalEntries) -} PSP_DIRECTORY; - -#endif //_PSP_DIRECTORY_H_ |