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-rw-r--r--src/mainboard/lenovo/t400/romstage.c117
-rw-r--r--src/mainboard/lenovo/x200/romstage.c95
-rw-r--r--src/mainboard/roda/rk9/romstage.c93
-rw-r--r--src/northbridge/intel/gm45/Makefile.inc1
-rw-r--r--src/northbridge/intel/gm45/gm45.h7
-rw-r--r--src/northbridge/intel/gm45/romstage.c135
6 files changed, 181 insertions, 267 deletions
diff --git a/src/mainboard/lenovo/t400/romstage.c b/src/mainboard/lenovo/t400/romstage.c
index 44f560bb6a..9f8993c5be 100644
--- a/src/mainboard/lenovo/t400/romstage.c
+++ b/src/mainboard/lenovo/t400/romstage.c
@@ -16,15 +16,7 @@
// __PRE_RAM__ means: use "unsigned" for device, not a struct.
-#include <stdint.h>
-#include <string.h>
#include <arch/io.h>
-#include <arch/acpi.h>
-#include <cpu/x86/lapic.h>
-#include <cpu/x86/tsc.h>
-#include <cpu/intel/romstage.h>
-#include <cbmem.h>
-#include <romstage_handoff.h>
#include <console/console.h>
#include <southbridge/intel/i82801ix/i82801ix.h>
#include <southbridge/intel/common/gpio.h>
@@ -33,7 +25,6 @@
#include "dock.h"
#define LPC_DEV PCI_DEV(0, 0x1f, 0)
-#define MCH_DEV PCI_DEV(0, 0, 0)
static void hybrid_graphics_init(sysinfo_t *sysinfo)
{
@@ -45,7 +36,9 @@ static void hybrid_graphics_init(sysinfo_t *sysinfo)
sysinfo->enable_peg = peg;
}
-static void early_lpc_setup(void)
+static int dock_err;
+
+void mb_setup_lpc(void)
{
/* Set up SuperIO LPC forwards */
@@ -59,99 +52,35 @@ static void early_lpc_setup(void)
pci_write_config32(LPC_DEV, D31F0_GEN3_DEC, 0x1c1681);
}
-void mainboard_romstage_entry(unsigned long bist)
+void mb_setup_superio(void)
{
- sysinfo_t sysinfo;
- int s3resume = 0;
- int cbmem_initted;
- int err;
- u16 reg16;
-
- /* basic northbridge setup, including MMCONF BAR */
- gm45_early_init();
-
- if (bist == 0)
- enable_lapic();
-
- /* First, run everything needed for console output. */
- i82801ix_early_init();
- early_lpc_setup();
-
/* Minimal setup to detect dock */
- err = pc87382_early();
- if (err == 0)
+ dock_err = pc87382_early();
+ if (dock_err == 0)
dock_connect();
+}
- console_init();
- printk(BIOS_DEBUG, "running main(bist = %lu)\n", bist);
+void get_mb_spd_addrmap(u8 *spd_addrmap)
+{
+ spd_addrmap[0] = 0x50;
+ spd_addrmap[2] = 0x51;
+}
- /* Print dock info */
- if (err)
+void mb_pre_raminit_setup(sysinfo_t *sysinfo)
+{
+ /* Console is not yet initialized in mb_setup_superio, so we print
+ the dock information here */
+ if (dock_err)
printk(BIOS_ERR, "DOCK: Failed to init pc87382\n");
else
dock_info();
- reg16 = pci_read_config16(LPC_DEV, D31F0_GEN_PMCON_3);
- pci_write_config16(LPC_DEV, D31F0_GEN_PMCON_3, reg16);
- if ((MCHBAR16(SSKPD_MCHBAR) == 0xCAFE) && !(reg16 & (1 << 9))) {
- printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n");
- gm45_early_reset();
- }
-
- setup_pch_gpios(&mainboard_gpio_map);
-
- /* ASPM related setting, set early by original BIOS. */
- DMIBAR16(0x204) &= ~(3 << 10);
-
- /* Check for S3 resume. */
- const u32 pm1_cnt = inl(DEFAULT_PMBASE + 0x04);
- if (((pm1_cnt >> 10) & 7) == 5) {
- if (acpi_s3_resume_allowed()) {
- printk(BIOS_DEBUG, "Resume from S3 detected.\n");
- s3resume = 1;
- /* Clear SLP_TYPE. This will break stage2 but
- * we care for that when we get there.
- */
- outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + 0x04);
- } else {
- printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
- }
- }
-
- /* RAM initialization */
- enter_raminit_or_reset();
- memset(&sysinfo, 0, sizeof(sysinfo));
- sysinfo.spd_map[0] = 0x50;
- sysinfo.spd_map[2] = 0x51;
- get_gmch_info(&sysinfo);
-
- /* Configure graphic GPIOs.
- * Make sure there's a little delay between
- * setup_pch_gpios() and this call ! */
- hybrid_graphics_init(&sysinfo);
-
- raminit(&sysinfo, s3resume);
-
- const u32 deven = pci_read_config32(MCH_DEV, D0F0_DEVEN);
- /* Disable D4F0 (unknown signal controller). */
- pci_write_config32(MCH_DEV, D0F0_DEVEN, deven & ~0x4000);
-
- init_pm(&sysinfo, 0);
-
- i82801ix_dmi_setup();
- gm45_late_init(sysinfo.stepping);
- i82801ix_dmi_poll_vc1();
-
- MCHBAR16(SSKPD_MCHBAR) = 0xCAFE;
-
- init_iommu();
+ hybrid_graphics_init(sysinfo);
+}
- /* FIXME: make a proper SMBUS mux support. */
+void mb_post_raminit_setup(void)
+{
+ /* FIXME: make a proper SMBUS mux support. */
+ /* Set the SMBUS mux to the eeprom */
set_gpio(42, GPIO_LEVEL_LOW);
-
- cbmem_initted = !cbmem_recovery(s3resume);
-
- romstage_handoff_init(cbmem_initted && s3resume);
-
- printk(BIOS_SPEW, "exit main()\n");
}
diff --git a/src/mainboard/lenovo/x200/romstage.c b/src/mainboard/lenovo/x200/romstage.c
index c0113562a1..e8bbfb09fd 100644
--- a/src/mainboard/lenovo/x200/romstage.c
+++ b/src/mainboard/lenovo/x200/romstage.c
@@ -16,27 +16,15 @@
// __PRE_RAM__ means: use "unsigned" for device, not a struct.
-#include <stdint.h>
-#include <string.h>
#include <arch/io.h>
-#include <arch/acpi.h>
-#include <cpu/x86/lapic.h>
-#include <cpu/x86/tsc.h>
-#include <cpu/intel/romstage.h>
-#include <cbmem.h>
-#include <romstage_handoff.h>
-#include <console/console.h>
#include <southbridge/intel/common/gpio.h>
#include <southbridge/intel/i82801ix/i82801ix.h>
#include <northbridge/intel/gm45/gm45.h>
#define LPC_DEV PCI_DEV(0, 0x1f, 0)
-#define MCH_DEV PCI_DEV(0, 0, 0)
-static void early_lpc_setup(void)
+void mb_setup_lpc(void)
{
- /* Set up SuperIO LPC forwards */
-
/* Configure serial IRQs.*/
pci_write_config8(LPC_DEV, D31F0_SERIRQ_CNTL, 0xd0);
/* Map COMa on 0x3f8, COMb on 0x2f8. */
@@ -47,82 +35,15 @@ static void early_lpc_setup(void)
pci_write_config32(LPC_DEV, D31F0_GEN3_DEC, 0x1c1681);
}
-void mainboard_romstage_entry(unsigned long bist)
+void get_mb_spd_addrmap(u8 *spd_addrmap)
{
- sysinfo_t sysinfo;
- int s3resume = 0;
- int cbmem_initted;
- u16 reg16;
-
- /* basic northbridge setup, including MMCONF BAR */
- gm45_early_init();
-
- if (bist == 0)
- enable_lapic();
-
- /* First, run everything needed for console output. */
- i82801ix_early_init();
- early_lpc_setup();
- console_init();
- printk(BIOS_DEBUG, "running main(bist = %lu)\n", bist);
-
- reg16 = pci_read_config16(LPC_DEV, D31F0_GEN_PMCON_3);
- pci_write_config16(LPC_DEV, D31F0_GEN_PMCON_3, reg16);
- if ((MCHBAR16(SSKPD_MCHBAR) == 0xCAFE) && !(reg16 & (1 << 9))) {
- printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n");
- gm45_early_reset();
- }
-
- setup_pch_gpios(&mainboard_gpio_map);
-
- /* ASPM related setting, set early by original BIOS. */
- DMIBAR16(0x204) &= ~(3 << 10);
-
- /* Check for S3 resume. */
- const u32 pm1_cnt = inl(DEFAULT_PMBASE + 0x04);
- if (((pm1_cnt >> 10) & 7) == 5) {
- if (acpi_s3_resume_allowed()) {
- printk(BIOS_DEBUG, "Resume from S3 detected.\n");
- s3resume = 1;
- /* Clear SLP_TYPE. This will break stage2 but
- * we care for that when we get there.
- */
- outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + 0x04);
- } else {
- printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
- }
- }
-
- /* RAM initialization */
- enter_raminit_or_reset();
- memset(&sysinfo, 0, sizeof(sysinfo));
- sysinfo.spd_map[0] = 0x50;
- sysinfo.spd_map[2] = 0x51;
- sysinfo.enable_igd = 1;
- sysinfo.enable_peg = 0;
- get_gmch_info(&sysinfo);
- raminit(&sysinfo, s3resume);
-
- const u32 deven = pci_read_config32(MCH_DEV, D0F0_DEVEN);
- /* Disable D4F0 (unknown signal controller). */
- pci_write_config32(MCH_DEV, D0F0_DEVEN, deven & ~0x4000);
-
- init_pm(&sysinfo, 0);
-
- i82801ix_dmi_setup();
- gm45_late_init(sysinfo.stepping);
- i82801ix_dmi_poll_vc1();
-
- MCHBAR16(SSKPD_MCHBAR) = 0xCAFE;
-
- init_iommu();
+ spd_addrmap[0] = 0x50;
+ spd_addrmap[2] = 0x51;
+}
+void mb_post_raminit_setup(void)
+{
/* FIXME: make a proper SMBUS mux support. */
+ /* Set the SMBUS mux to the eeprom */
set_gpio(42, GPIO_LEVEL_LOW);
-
- cbmem_initted = !cbmem_recovery(s3resume);
-
- romstage_handoff_init(cbmem_initted && s3resume);
-
- printk(BIOS_SPEW, "exit main()\n");
}
diff --git a/src/mainboard/roda/rk9/romstage.c b/src/mainboard/roda/rk9/romstage.c
index ff8bc874c5..742e2eec85 100644
--- a/src/mainboard/roda/rk9/romstage.c
+++ b/src/mainboard/roda/rk9/romstage.c
@@ -16,17 +16,7 @@
/* __PRE_RAM__ means: use "unsigned" for device, not a struct. */
-#include <stdint.h>
-#include <string.h>
#include <arch/io.h>
-#include <cpu/x86/lapic.h>
-#include <cpu/x86/msr.h>
-#include <cpu/x86/tsc.h>
-#include <cpu/intel/romstage.h>
-#include <arch/acpi.h>
-#include <cbmem.h>
-#include <romstage_handoff.h>
-#include <console/console.h>
#include <southbridge/intel/common/gpio.h>
#include <southbridge/intel/i82801ix/i82801ix.h>
#include <northbridge/intel/gm45/gm45.h>
@@ -35,7 +25,7 @@
#define LPC_DEV PCI_DEV(0, 0x1f, 0)
#define SERIAL_DEV PNP_DEV(0x2e, LPC47N227_SP1)
-static void early_lpc_setup(void)
+void mb_setup_lpc(void)
{
/* Set up SuperIO LPC forwards */
@@ -47,7 +37,7 @@ static void early_lpc_setup(void)
pci_write_config16(LPC_DEV, D31F0_LPC_EN, 0x3c03);
}
-static void default_superio_gpio_setup(void)
+void mb_setup_superio(void)
{
/* Original settings:
idx 30 31 32 33 34 35 36 37 38 39
@@ -87,81 +77,12 @@ static void default_superio_gpio_setup(void)
/* Set GPIO output values: */
outb(0x88, 0x600 + 0xb + 3); /* GP30 - GP37 */
outb(0x10, 0x600 + 0xb + 4); /* GP40 - GP47 */
+
+ lpc47n227_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
}
-void mainboard_romstage_entry(unsigned long bist)
+void get_mb_spd_addrmap(u8 *spd_addrmap)
{
- sysinfo_t sysinfo;
- int s3resume = 0;
- int cbmem_initted;
- u16 reg16;
-
- /* basic northbridge setup, including MMCONF BAR */
- gm45_early_init();
-
- if (bist == 0)
- enable_lapic();
-
- /* First, run everything needed for console output. */
- i82801ix_early_init();
- early_lpc_setup();
- default_superio_gpio_setup();
- lpc47n227_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
- console_init();
- printk(BIOS_DEBUG, "running main(bist = %lu)\n", bist);
-
- reg16 = pci_read_config16(LPC_DEV, D31F0_GEN_PMCON_3);
- pci_write_config16(LPC_DEV, D31F0_GEN_PMCON_3, reg16);
- if ((MCHBAR16(SSKPD_MCHBAR) == 0xCAFE) && !(reg16 & (1 << 9))) {
- printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n");
- gm45_early_reset();
- }
-
- setup_pch_gpios(&mainboard_gpio_map);
-
- /* ASPM related setting, set early by original BIOS. */
- DMIBAR16(0x204) &= ~(3 << 10);
-
- /* Check for S3 resume. */
- const u32 pm1_cnt = inl(DEFAULT_PMBASE + 0x04);
- if (((pm1_cnt >> 10) & 7) == 5) {
- if (acpi_s3_resume_allowed()) {
- printk(BIOS_DEBUG, "Resume from S3 detected.\n");
- s3resume = 1;
- /* Clear SLP_TYPE. This will break stage2 but
- * we care for that when we get there.
- */
- outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + 0x04);
- } else {
- printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
- }
- }
-
- /* RAM initialization */
- enter_raminit_or_reset();
- memset(&sysinfo, 0, sizeof(sysinfo));
- get_gmch_info(&sysinfo);
- sysinfo.spd_map[0] = 0x50;
- sysinfo.spd_map[1] = 0;
- sysinfo.spd_map[2] = 0x52;
- sysinfo.spd_map[3] = 0;
- sysinfo.enable_igd = 1;
- sysinfo.enable_peg = 0;
- raminit(&sysinfo, s3resume);
-
- init_pm(&sysinfo, 1);
-
- i82801ix_dmi_setup();
- gm45_late_init(sysinfo.stepping);
- i82801ix_dmi_poll_vc1();
-
- MCHBAR16(SSKPD_MCHBAR) = 0xCAFE;
-
- init_iommu();
-
- cbmem_initted = !cbmem_recovery(s3resume);
-
- romstage_handoff_init(cbmem_initted && s3resume);
-
- printk(BIOS_SPEW, "exit main()\n");
+ spd_addrmap[0] = 0x50;
+ spd_addrmap[2] = 0x52;
}
diff --git a/src/northbridge/intel/gm45/Makefile.inc b/src/northbridge/intel/gm45/Makefile.inc
index 95b360ce4c..16a9ddb648 100644
--- a/src/northbridge/intel/gm45/Makefile.inc
+++ b/src/northbridge/intel/gm45/Makefile.inc
@@ -27,6 +27,7 @@ romstage-y += igd.c
romstage-y += pm.c
romstage-y += ram_calc.c
romstage-y += iommu.c
+romstage-y += romstage.c
ramstage-y += acpi.c
diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h
index 736d6af6bd..0096793c23 100644
--- a/src/northbridge/intel/gm45/gm45.h
+++ b/src/northbridge/intel/gm45/gm45.h
@@ -436,6 +436,13 @@ u32 decode_tseg_size(u8 esmramc);
void init_iommu(void);
+/* romstage mainboard hookups */
+void mb_setup_lpc(void);
+void mb_setup_superio(void); /* optional */
+void get_mb_spd_addrmap(u8 spd_addrmap[4]);
+void mb_pre_raminit_setup(sysinfo_t *); /* optional */
+void mb_post_raminit_setup(void); /* optional */
+
struct blc_pwm_t {
char ascii_string[13];
int pwm_freq; /* In Hz */
diff --git a/src/northbridge/intel/gm45/romstage.c b/src/northbridge/intel/gm45/romstage.c
new file mode 100644
index 0000000000..6d652bb8d8
--- /dev/null
+++ b/src/northbridge/intel/gm45/romstage.c
@@ -0,0 +1,135 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2010 coresystems GmbH
+ * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
+ * Copyright (C) 2014 Vladimir Serbinenko
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <cbmem.h>
+#include <romstage_handoff.h>
+#include <console/console.h>
+#include <arch/io.h>
+#include <arch/acpi.h>
+#include <cpu/x86/lapic.h>
+#include <cpu/x86/bist.h>
+#include <cpu/intel/romstage.h>
+#include <northbridge/intel/gm45/gm45.h>
+#include <southbridge/intel/i82801ix/i82801ix.h>
+#include <southbridge/intel/common/gpio.h>
+
+#define LPC_DEV PCI_DEV(0, 0x1f, 0)
+#define MCH_DEV PCI_DEV(0, 0, 0)
+
+void __weak mb_setup_superio(void)
+{
+}
+
+void __weak mb_pre_raminit_setup(sysinfo_t *sysinfo)
+{
+}
+
+void __weak mb_post_raminit_setup(void)
+{
+}
+
+/* Platform has no romstage entry point under mainboard directory,
+ * so this one is named with prefix mainboard.
+ */
+void mainboard_romstage_entry(unsigned long bist)
+{
+ sysinfo_t sysinfo;
+ int s3resume = 0;
+ int cbmem_initted;
+ u16 reg16;
+
+ /* basic northbridge setup, including MMCONF BAR */
+ gm45_early_init();
+
+ if (bist == 0)
+ enable_lapic();
+
+ /* First, run everything needed for console output. */
+ i82801ix_early_init();
+ setup_pch_gpios(&mainboard_gpio_map);
+
+ mb_setup_lpc();
+
+ mb_setup_superio();
+
+ console_init();
+ report_bist_failure(bist);
+
+ reg16 = pci_read_config16(LPC_DEV, D31F0_GEN_PMCON_3);
+ pci_write_config16(LPC_DEV, D31F0_GEN_PMCON_3, reg16);
+ if ((MCHBAR16(SSKPD_MCHBAR) == 0xCAFE) && !(reg16 & (1 << 9))) {
+ printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n");
+ gm45_early_reset();
+ }
+
+ /* ASPM related setting, set early by original BIOS. */
+ DMIBAR16(0x204) &= ~(3 << 10);
+
+ /* Check for S3 resume. */
+ const u32 pm1_cnt = inl(DEFAULT_PMBASE + 0x04);
+ if (((pm1_cnt >> 10) & 7) == 5) {
+ if (acpi_s3_resume_allowed()) {
+ printk(BIOS_DEBUG, "Resume from S3 detected.\n");
+ s3resume = 1;
+ /* Clear SLP_TYPE. This will break stage2 but
+ * we care for that when we get there.
+ */
+ outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + 0x04);
+ } else {
+ printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
+ }
+ }
+
+ /* RAM initialization */
+ enter_raminit_or_reset();
+ memset(&sysinfo, 0, sizeof(sysinfo));
+ get_mb_spd_addrmap(sysinfo.spd_map);
+ const struct device *dev;
+ dev = pcidev_on_root(2, 0);
+ if (dev)
+ sysinfo.enable_igd = dev->enabled;
+ dev = pcidev_on_root(1, 0);
+ if (dev)
+ sysinfo.enable_peg = dev->enabled;
+ get_gmch_info(&sysinfo);
+
+ mb_pre_raminit_setup(&sysinfo);
+
+ raminit(&sysinfo, s3resume);
+
+ mb_post_raminit_setup();
+
+ const u32 deven = pci_read_config32(MCH_DEV, D0F0_DEVEN);
+ /* Disable D4F0 (unknown signal controller). */
+ pci_write_config32(MCH_DEV, D0F0_DEVEN, deven & ~0x4000);
+
+ init_pm(&sysinfo, 0);
+
+ i82801ix_dmi_setup();
+ gm45_late_init(sysinfo.stepping);
+ i82801ix_dmi_poll_vc1();
+
+ MCHBAR16(SSKPD_MCHBAR) = 0xCAFE;
+
+ init_iommu();
+
+ cbmem_initted = !cbmem_recovery(s3resume);
+
+ romstage_handoff_init(cbmem_initted && s3resume);
+
+ printk(BIOS_SPEW, "exit main()\n");
+}
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-22 18:34:46 +0000