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-rw-r--r--src/soc/intel/alderlake/cpu.c21
-rw-r--r--src/soc/intel/apollolake/Makefile.inc1
-rw-r--r--src/soc/intel/apollolake/include/soc/pm.h2
-rw-r--r--src/soc/intel/apollolake/pmutil.c18
-rw-r--r--src/soc/intel/cannonlake/cpu.c25
-rw-r--r--src/soc/intel/common/block/cpu/Makefile.inc1
-rw-r--r--src/soc/intel/common/block/cpu/pm_timer_emulation.c26
-rw-r--r--src/soc/intel/common/block/include/intelblocks/cpulib.h6
-rw-r--r--src/soc/intel/elkhartlake/cpu.c21
-rw-r--r--src/soc/intel/icelake/cpu.c21
-rw-r--r--src/soc/intel/jasperlake/cpu.c21
-rw-r--r--src/soc/intel/skylake/cpu.c24
-rw-r--r--src/soc/intel/tigerlake/cpu.c21
13 files changed, 34 insertions, 174 deletions
diff --git a/src/soc/intel/alderlake/cpu.c b/src/soc/intel/alderlake/cpu.c
index 39a42651bd..9fab277781 100644
--- a/src/soc/intel/alderlake/cpu.c
+++ b/src/soc/intel/alderlake/cpu.c
@@ -23,7 +23,6 @@
#include <soc/cpu.h>
#include <soc/msr.h>
#include <soc/pci_devs.h>
-#include <soc/pm.h>
#include <soc/soc_chip.h>
static void soc_fsp_load(void)
@@ -62,25 +61,6 @@ static void configure_misc(void)
wrmsr(MSR_POWER_CTL, msr);
}
-static void enable_pm_timer_emulation(void)
-{
- msr_t msr;
-
- if (!CONFIG_CPU_XTAL_HZ)
- return;
-
- /*
- * The derived frequency is calculated as follows:
- * (clock * msr[63:32]) >> 32 = target frequency.
- * Back solve the multiplier so the 3.579545MHz ACPI timer frequency is used.
- */
- msr.hi = (3579545ULL << 32) / CONFIG_CPU_XTAL_HZ;
- /* Set PM1 timer IO port and enable */
- msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) |
- EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR);
- wrmsr(MSR_EMULATE_PM_TIMER, msr);
-}
-
/* All CPUs including BSP will run the following function. */
void soc_core_init(struct device *cpu)
{
@@ -97,7 +77,6 @@ void soc_core_init(struct device *cpu)
/* Configure Enhanced SpeedStep and Thermal Sensors */
configure_misc();
- /* Enable PM timer emulation */
enable_pm_timer_emulation();
/* Enable Direct Cache Access */
diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc
index 79fab1a9d1..64889e56f9 100644
--- a/src/soc/intel/apollolake/Makefile.inc
+++ b/src/soc/intel/apollolake/Makefile.inc
@@ -10,6 +10,7 @@ subdirs-y += ../../../cpu/x86/tsc
subdirs-y += ../../../cpu/x86/cache
bootblock-y += bootblock/bootblock.c
+bootblock-y += ../common/block/cpu/pm_timer_emulation.c
bootblock-$(CONFIG_FSP_CAR) += fspcar.c
bootblock-y += car.c
bootblock-y += heci.c
diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h
index aaf62583e6..748f76adba 100644
--- a/src/soc/intel/apollolake/include/soc/pm.h
+++ b/src/soc/intel/apollolake/include/soc/pm.h
@@ -234,8 +234,6 @@ struct chipset_power_state {
void pch_log_state(void);
-void enable_pm_timer_emulation(void);
-
/* STM Support */
uint16_t get_pmbase(void);
diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c
index e0de93eae4..6e96b57a07 100644
--- a/src/soc/intel/apollolake/pmutil.c
+++ b/src/soc/intel/apollolake/pmutil.c
@@ -178,24 +178,6 @@ int soc_prev_sleep_state(const struct chipset_power_state *ps,
return prev_sleep_state;
}
-void enable_pm_timer_emulation(void)
-{
- msr_t msr;
-
- if (!CONFIG_CPU_XTAL_HZ)
- return;
-
- /*
- * The derived frequency is calculated as follows:
- * (clock * msr[63:32]) >> 32 = target frequency.
- * Back solve the multiplier so the 3.579545MHz ACPI timer frequency is used.
- */
- msr.hi = (3579545ULL << 32) / CONFIG_CPU_XTAL_HZ;
- /* Set PM1 timer IO port and enable */
- msr.lo = EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + R_ACPI_PM1_TMR);
- wrmsr(MSR_EMULATE_PM_TIMER, msr);
-}
-
static int rtc_failed(uint32_t gen_pmcon1)
{
return !!(gen_pmcon1 & RPS);
diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c
index 20da942f84..61b19894eb 100644
--- a/src/soc/intel/cannonlake/cpu.c
+++ b/src/soc/intel/cannonlake/cpu.c
@@ -14,7 +14,6 @@
#include <soc/cpu.h>
#include <soc/msr.h>
#include <soc/pci_devs.h>
-#include <soc/pm.h>
#include <soc/systemagent.h>
#include <cpu/x86/mtrr.h>
#include <cpu/intel/microcode.h>
@@ -58,29 +57,6 @@ static void configure_misc(void)
wrmsr(MSR_POWER_CTL, msr);
}
-/*
- * The emulated ACPI timer allows replacing of the ACPI timer
- * (PM1_TMR) to have no impart on the system.
- */
-static void enable_pm_timer_emulation(void)
-{
- msr_t msr;
-
- if (!CONFIG_CPU_XTAL_HZ)
- return;
-
- /*
- * The derived frequency is calculated as follows:
- * (clock * msr[63:32]) >> 32 = target frequency.
- * Back solve the multiplier so the 3.579545MHz ACPI timer frequency is used.
- */
- msr.hi = (3579545ULL << 32) / CONFIG_CPU_XTAL_HZ;
- /* Set PM1 timer IO port and enable */
- msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) |
- EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR);
- wrmsr(MSR_EMULATE_PM_TIMER, msr);
-}
-
static void configure_c_states(void)
{
msr_t msr;
@@ -135,7 +111,6 @@ void soc_core_init(struct device *cpu)
set_aesni_lock();
- /* Enable ACPI Timer Emulation via MSR 0x121 */
enable_pm_timer_emulation();
/* Enable Direct Cache Access */
diff --git a/src/soc/intel/common/block/cpu/Makefile.inc b/src/soc/intel/common/block/cpu/Makefile.inc
index deddb67a16..7692076375 100644
--- a/src/soc/intel/common/block/cpu/Makefile.inc
+++ b/src/soc/intel/common/block/cpu/Makefile.inc
@@ -11,3 +11,4 @@ bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU) += cpulib.c
romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU) += cpulib.c
ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU) += cpulib.c
ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_MPINIT) += mp_init.c
+ramstage-$(CONFIG_CPU_SUPPORTS_PM_TIMER_EMULATION) += pm_timer_emulation.c
diff --git a/src/soc/intel/common/block/cpu/pm_timer_emulation.c b/src/soc/intel/common/block/cpu/pm_timer_emulation.c
new file mode 100644
index 0000000000..8f56da54c5
--- /dev/null
+++ b/src/soc/intel/common/block/cpu/pm_timer_emulation.c
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <cpu/x86/msr.h>
+#include <intelblocks/cpulib.h>
+#include <intelblocks/msr.h>
+#include <soc/iomap.h>
+#include <soc/pm.h>
+
+void enable_pm_timer_emulation(void)
+{
+ msr_t msr;
+
+ if (!CONFIG_CPU_XTAL_HZ)
+ return;
+
+ /*
+ * The derived frequency is calculated as follows:
+ * (clock * msr[63:32]) >> 32 = target frequency.
+ * Back solve the multiplier so the 3.579545MHz ACPI timer frequency is used.
+ */
+ msr.hi = (3579545ULL << 32) / CONFIG_CPU_XTAL_HZ;
+ /* Set PM1 timer IO port and enable */
+ msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) |
+ EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR);
+ wrmsr(MSR_EMULATE_PM_TIMER, msr);
+}
diff --git a/src/soc/intel/common/block/include/intelblocks/cpulib.h b/src/soc/intel/common/block/include/intelblocks/cpulib.h
index d2b00efb2f..4dfbef48f6 100644
--- a/src/soc/intel/common/block/include/intelblocks/cpulib.h
+++ b/src/soc/intel/common/block/include/intelblocks/cpulib.h
@@ -156,4 +156,10 @@ void cpu_lt_lock_memory(void *unused);
/* Get a supported PRMRR size in bytes with respect to users choice */
int get_valid_prmrr_size(void);
+/*
+ * Enable the emulated ACPI timer in case it's not available or to allow
+ * disabling the PM ACPI timer (PM1_TMR) for power saving.
+ */
+void enable_pm_timer_emulation(void);
+
#endif /* SOC_INTEL_COMMON_BLOCK_CPULIB_H */
diff --git a/src/soc/intel/elkhartlake/cpu.c b/src/soc/intel/elkhartlake/cpu.c
index 720a295e15..d0fa019ef8 100644
--- a/src/soc/intel/elkhartlake/cpu.c
+++ b/src/soc/intel/elkhartlake/cpu.c
@@ -17,7 +17,6 @@
#include <soc/cpu.h>
#include <soc/msr.h>
#include <soc/pci_devs.h>
-#include <soc/pm.h>
#include <soc/soc_chip.h>
static void soc_fsp_load(void)
@@ -56,25 +55,6 @@ static void configure_misc(void)
wrmsr(MSR_POWER_CTL, msr);
}
-static void enable_pm_timer_emulation(void)
-{
- msr_t msr;
-
- if (!CONFIG_CPU_XTAL_HZ)
- return;
-
- /*
- * The derived frequency is calculated as follows:
- * (clock * msr[63:32]) >> 32 = target frequency.
- * Back solve the multiplier so the 3.579545MHz ACPI timer frequency is used.
- */
- msr.hi = (3579545ULL << 32) / CONFIG_CPU_XTAL_HZ;
- /* Set PM1 timer IO port and enable */
- msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) |
- EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR);
- wrmsr(MSR_EMULATE_PM_TIMER, msr);
-}
-
/* All CPUs including BSP will run the following function. */
void soc_core_init(struct device *cpu)
{
@@ -91,7 +71,6 @@ void soc_core_init(struct device *cpu)
/* Configure Enhanced SpeedStep and Thermal Sensors */
configure_misc();
- /* Enable PM timer emulation */
enable_pm_timer_emulation();
/* Enable Direct Cache Access */
diff --git a/src/soc/intel/icelake/cpu.c b/src/soc/intel/icelake/cpu.c
index ea2b3574b2..1734ba6c30 100644
--- a/src/soc/intel/icelake/cpu.c
+++ b/src/soc/intel/icelake/cpu.c
@@ -17,7 +17,6 @@
#include <soc/cpu.h>
#include <soc/msr.h>
#include <soc/pci_devs.h>
-#include <soc/pm.h>
#include <soc/soc_chip.h>
static void soc_fsp_load(void)
@@ -56,25 +55,6 @@ static void configure_misc(void)
wrmsr(MSR_POWER_CTL, msr);
}
-static void enable_pm_timer_emulation(void)
-{
- msr_t msr;
-
- if (!CONFIG_CPU_XTAL_HZ)
- return;
-
- /*
- * The derived frequency is calculated as follows:
- * (clock * msr[63:32]) >> 32 = target frequency.
- * Back solve the multiplier so the 3.579545MHz ACPI timer frequency is used.
- */
- msr.hi = (3579545ULL << 32) / CONFIG_CPU_XTAL_HZ;
- /* Set PM1 timer IO port and enable */
- msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) |
- EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR);
- wrmsr(MSR_EMULATE_PM_TIMER, msr);
-}
-
static void configure_c_states(void)
{
msr_t msr;
@@ -127,7 +107,6 @@ void soc_core_init(struct device *cpu)
/* Configure Enhanced SpeedStep and Thermal Sensors */
configure_misc();
- /* Enable PM timer emulation */
enable_pm_timer_emulation();
/* Enable Direct Cache Access */
diff --git a/src/soc/intel/jasperlake/cpu.c b/src/soc/intel/jasperlake/cpu.c
index 312fc7d7af..6518945d8d 100644
--- a/src/soc/intel/jasperlake/cpu.c
+++ b/src/soc/intel/jasperlake/cpu.c
@@ -17,7 +17,6 @@
#include <soc/cpu.h>
#include <soc/msr.h>
#include <soc/pci_devs.h>
-#include <soc/pm.h>
#include <soc/soc_chip.h>
static void soc_fsp_load(void)
@@ -56,25 +55,6 @@ static void configure_misc(void)
wrmsr(MSR_POWER_CTL, msr);
}
-static void enable_pm_timer_emulation(void)
-{
- msr_t msr;
-
- if (!CONFIG_CPU_XTAL_HZ)
- return;
-
- /*
- * The derived frequency is calculated as follows:
- * (clock * msr[63:32]) >> 32 = target frequency.
- * Back solve the multiplier so the 3.579545MHz ACPI timer frequency is used.
- */
- msr.hi = (3579545ULL << 32) / CONFIG_CPU_XTAL_HZ;
- /* Set PM1 timer IO port and enable */
- msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) |
- EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR);
- wrmsr(MSR_EMULATE_PM_TIMER, msr);
-}
-
/* All CPUs including BSP will run the following function. */
void soc_core_init(struct device *cpu)
{
@@ -91,7 +71,6 @@ void soc_core_init(struct device *cpu)
/* Configure Enhanced SpeedStep and Thermal Sensors */
configure_misc();
- /* Enable PM timer emulation */
enable_pm_timer_emulation();
/* Enable Direct Cache Access */
diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c
index 1682503d4b..6872c12101 100644
--- a/src/soc/intel/skylake/cpu.c
+++ b/src/soc/intel/skylake/cpu.c
@@ -21,7 +21,6 @@
#include <soc/cpu.h>
#include <soc/msr.h>
#include <soc/pci_devs.h>
-#include <soc/pm.h>
#include <soc/ramstage.h>
#include <soc/systemagent.h>
@@ -96,29 +95,6 @@ static void configure_c_states(void)
wrmsr(MSR_C_STATE_LATENCY_CONTROL_5, msr);
}
-/*
- * The emulated ACPI timer allows disabling of the ACPI timer
- * (PM1_TMR) to have no impart on the system.
- */
-static void enable_pm_timer_emulation(void)
-{
- msr_t msr;
-
- if (!CONFIG_CPU_XTAL_HZ)
- return;
-
- /*
- * The derived frequency is calculated as follows:
- * (clock * msr[63:32]) >> 32 = target frequency.
- * Back solve the multiplier so the 3.579545MHz ACPI timer frequency is used.
- */
- msr.hi = (3579545ULL << 32) / CONFIG_CPU_XTAL_HZ;
- /* Set PM1 timer IO port and enable */
- msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) |
- EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR);
- wrmsr(MSR_EMULATE_PM_TIMER, msr);
-}
-
/* All CPUs including BSP will run the following function. */
void soc_core_init(struct device *cpu)
{
diff --git a/src/soc/intel/tigerlake/cpu.c b/src/soc/intel/tigerlake/cpu.c
index d7234e7191..36dfa1b738 100644
--- a/src/soc/intel/tigerlake/cpu.c
+++ b/src/soc/intel/tigerlake/cpu.c
@@ -23,7 +23,6 @@
#include <soc/cpu.h>
#include <soc/msr.h>
#include <soc/pci_devs.h>
-#include <soc/pm.h>
#include <soc/soc_chip.h>
static void soc_fsp_load(void)
@@ -62,25 +61,6 @@ static void configure_misc(void)
wrmsr(MSR_POWER_CTL, msr);
}
-static void enable_pm_timer_emulation(void)
-{
- msr_t msr;
-
- if (!CONFIG_CPU_XTAL_HZ)
- return;
-
- /*
- * The derived frequency is calculated as follows:
- * (clock * msr[63:32]) >> 32 = target frequency.
- * Back solve the multiplier so the 3.579545MHz ACPI timer frequency is used.
- */
- msr.hi = (3579545ULL << 32) / CONFIG_CPU_XTAL_HZ;
- /* Set PM1 timer IO port and enable */
- msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) |
- EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR);
- wrmsr(MSR_EMULATE_PM_TIMER, msr);
-}
-
/* All CPUs including BSP will run the following function. */
void soc_core_init(struct device *cpu)
{
@@ -97,7 +77,6 @@ void soc_core_init(struct device *cpu)
/* Configure Enhanced SpeedStep and Thermal Sensors */
configure_misc();
- /* Enable PM timer emulation */
enable_pm_timer_emulation();
/* Enable Direct Cache Access */
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-25 01:35:10 +0000