diff options
| -rw-r--r-- | src/mainboard/google/volteer/variants/baseboard/devicetree.cb | 8 | ||||
| -rw-r--r-- | src/soc/intel/tigerlake/chip.h | 7 | ||||
| -rw-r--r-- | src/soc/intel/tigerlake/systemagent.c | 28 |
3 files changed, 40 insertions, 3 deletions
diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 8cd926cd88..f2e427f0bb 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -198,9 +198,15 @@ chip soc/intel/tigerlake # Enable DPTF register "dptf_enable" = "1" - register "power_limits_config" = "{ + register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{ .tdp_pl1_override = 15, .tdp_pl2_override = 60, + .tdp_pl4 = 105, + }" + register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{ + .tdp_pl1_override = 15, + .tdp_pl2_override = 38, + .tdp_pl4 = 71, }" register "Device4Enable" = "1" diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index 30377aaf79..8b1fe2d03f 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -22,6 +22,11 @@ #define MAX_HD_AUDIO_SNDW_LINKS 4 #define MAX_HD_AUDIO_SSP_LINKS 6 +/* The first two are for TGL-U */ +#define POWER_LIMITS_U_4_CORE 0 +#define POWER_LIMITS_U_2_CORE 1 +#define POWER_LIMITS_MAX 2 + /* * Enable External V1P05 Rail in: BIT0:S0i1/S0i2, * BIT1:S0i3, BIT2:S3, BIT3:S4, BIT4:S5 @@ -55,7 +60,7 @@ struct soc_intel_tigerlake_config { struct soc_intel_common_config common_soc_config; /* Common struct containing power limits configuration information */ - struct soc_power_limits_config power_limits_config; + struct soc_power_limits_config power_limits_config[POWER_LIMITS_MAX]; /* Gpio group routed to each dword of the GPE0 block. Values are * of the form PMC_GPP_[A:U] or GPD. */ diff --git a/src/soc/intel/tigerlake/systemagent.c b/src/soc/intel/tigerlake/systemagent.c index 08d1ef387c..e428365c4d 100644 --- a/src/soc/intel/tigerlake/systemagent.c +++ b/src/soc/intel/tigerlake/systemagent.c @@ -6,9 +6,11 @@ * Chapter number: 3 */ +#include <console/console.h> #include <device/device.h> #include <delay.h> #include <device/pci.h> +#include <device/pci_ids.h> #include <device/pci_ops.h> #include <intelblocks/power_limit.h> #include <intelblocks/systemagent.h> @@ -53,8 +55,14 @@ void soc_add_fixed_mmio_resources(struct device *dev, int *index) void soc_systemagent_init(struct device *dev) { struct soc_power_limits_config *soc_config; + struct device *sa; + uint16_t sa_pci_id; config_t *config; + /* Get System Agent PCI ID */ + sa = pcidev_path_on_root(SA_DEVFN_ROOT); + sa_pci_id = sa ? pci_read_config16(sa, PCI_DEVICE_ID) : 0xFFFF; + /* Enable Power Aware Interrupt Routing */ enable_power_aware_intr(); @@ -64,7 +72,25 @@ void soc_systemagent_init(struct device *dev) /* Configure turbo power limits 1ms after reset complete bit */ mdelay(1); config = config_of_soc(); - soc_config = &config->power_limits_config; + + /* + * Choose a power limits configuration based on the SoC SKU, + * differentiated here based on SA PCI ID. + */ + switch (sa_pci_id) { + case PCI_DEVICE_ID_INTEL_TGL_ID_U: + case PCI_DEVICE_ID_INTEL_TGL_ID_U_1: + soc_config = &config->power_limits_config[POWER_LIMITS_U_4_CORE]; + break; + case PCI_DEVICE_ID_INTEL_TGL_ID_U_2_2: + soc_config = &config->power_limits_config[POWER_LIMITS_U_2_CORE]; + break; + default: + printk(BIOS_ERR, "TGL: unknown SA ID: 0x%4x, skipping power limits " + "configuration\n", sa_pci_id); + return; + } + set_power_limits(MOBILE_SKU_PL1_TIME_SEC, soc_config); } |