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-rw-r--r--src/northbridge/intel/sandybridge/gma.c27
-rw-r--r--src/southbridge/intel/bd82x6x/lpc.c6
2 files changed, 27 insertions, 6 deletions
diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c
index dcc992c940..868a961fb8 100644
--- a/src/northbridge/intel/sandybridge/gma.c
+++ b/src/northbridge/intel/sandybridge/gma.c
@@ -24,6 +24,8 @@
#include <device/pci_ops.h>
#include <cpu/x86/msr.h>
#include <cpu/x86/mtrr.h>
+#include <southbridge/intel/bd82x6x/nvs.h>
+#include <cbmem.h>
#include "chip.h"
#include "sandybridge.h"
@@ -649,6 +651,30 @@ static void gma_ssdt(device_t device)
drivers_intel_gma_displays_ssdt_generate(gfx);
}
+static unsigned long
+gma_write_acpi_tables(struct device *const dev,
+ unsigned long current,
+ struct acpi_rsdp *const rsdp)
+{
+ igd_opregion_t *opregion;
+ global_nvs_t *gnvs;
+
+ // FIXME: Replace by common VBT implementation writing to current
+ opregion = igd_make_opregion();
+ if (opregion) {
+ /* GNVS has been already set up */
+ gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
+ if (gnvs) {
+ /* IGD OpRegion Base Address */
+ gnvs->aslb = (u32)(uintptr_t)opregion;
+ } else {
+ printk(BIOS_ERR, "Error: GNVS table not found.\n");
+ }
+ }
+
+ return current;
+}
+
/* called by pci set_vga_bridge function */
static void gma_func0_disable(struct device *dev)
{
@@ -676,6 +702,7 @@ static struct device_operations gma_func0_ops = {
.enable = 0,
.disable = gma_func0_disable,
.ops_pci = &gma_pci_ops,
+ .write_acpi_tables = gma_write_acpi_tables,
};
static const unsigned short pci_device_ids[] = { 0x0102, 0x0106, 0x010a, 0x0112,
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c
index 623482e679..c9fee89062 100644
--- a/src/southbridge/intel/bd82x6x/lpc.c
+++ b/src/southbridge/intel/bd82x6x/lpc.c
@@ -654,10 +654,6 @@ static void set_subsystem(device_t dev, unsigned vendor, unsigned device)
static void southbridge_inject_dsdt(device_t dev)
{
global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof(*gnvs));
- void *opregion;
-
- /* Calling northbridge code as gnvs contains opregion address. */
- opregion = igd_make_opregion();
if (gnvs) {
const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info();
@@ -676,8 +672,6 @@ static void southbridge_inject_dsdt(device_t dev)
chromeos_init_vboot(&(gnvs->chromeos));
#endif
- /* IGD OpRegion Base Address */
- gnvs->aslb = (u32)opregion;
/* And tell SMI about it */
smm_setup_structures(gnvs, NULL, NULL);