diff options
| -rw-r--r-- | src/soc/intel/broadwell/pch/me.c | 8 | ||||
| -rw-r--r-- | src/southbridge/intel/bd82x6x/me_common.c | 11 | ||||
| -rw-r--r-- | src/southbridge/intel/lynxpoint/me_9.x.c | 8 |
3 files changed, 8 insertions, 19 deletions
diff --git a/src/soc/intel/broadwell/pch/me.c b/src/soc/intel/broadwell/pch/me.c index 40a81d8810..88d2172be9 100644 --- a/src/soc/intel/broadwell/pch/me.c +++ b/src/soc/intel/broadwell/pch/me.c @@ -28,10 +28,7 @@ #include <soc/rcba.h> #include <soc/intel/broadwell/pch/chip.h> -#if CONFIG(CHROMEOS) #include <vendorcode/google/chromeos/chromeos.h> -#include <vendorcode/google/chromeos/gnvs.h> -#endif /* Path that the BIOS should take based on ME state */ static const char *me_bios_path_values[] = { @@ -772,10 +769,9 @@ static int intel_me_extend_valid(struct device *dev) } printk(BIOS_DEBUG, "\n"); -#if CONFIG(CHROMEOS) /* Save hash in NVS for the OS to verify */ - chromeos_set_me_hash(extend, count); -#endif + if (CONFIG(CHROMEOS)) + chromeos_set_me_hash(extend, count); return 0; } diff --git a/src/southbridge/intel/bd82x6x/me_common.c b/src/southbridge/intel/bd82x6x/me_common.c index ae157d36c3..422c091001 100644 --- a/src/southbridge/intel/bd82x6x/me_common.c +++ b/src/southbridge/intel/bd82x6x/me_common.c @@ -15,6 +15,8 @@ #include "me.h" #include "pch.h" +#include <vendorcode/google/chromeos/chromeos.h> + /* Path that the BIOS should take based on ME state */ static const char *const me_bios_path_values[] = { [ME_NORMAL_BIOS_PATH] = "Normal", @@ -362,10 +364,6 @@ int intel_mei_setup(struct device *dev) return 0; } -#if CONFIG(CHROMEOS) -#include <vendorcode/google/chromeos/chromeos.h> -#endif - /* Read the Extend register hash of ME firmware */ int intel_me_extend_valid(struct device *dev) { @@ -405,10 +403,9 @@ int intel_me_extend_valid(struct device *dev) } printk(BIOS_DEBUG, "\n"); -#if CONFIG(CHROMEOS) /* Save hash in NVS for the OS to verify */ - chromeos_set_me_hash(extend, count); -#endif + if (CONFIG(CHROMEOS)) + chromeos_set_me_hash(extend, count); return 0; } diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me_9.x.c index 9910658b82..69192e6ccb 100644 --- a/src/southbridge/intel/lynxpoint/me_9.x.c +++ b/src/southbridge/intel/lynxpoint/me_9.x.c @@ -25,10 +25,7 @@ #include "me.h" #include "pch.h" -#if CONFIG(CHROMEOS) #include <vendorcode/google/chromeos/chromeos.h> -#include <vendorcode/google/chromeos/gnvs.h> -#endif /* Path that the BIOS should take based on ME state */ static const char *const me_bios_path_values[] __unused = { @@ -755,10 +752,9 @@ static int intel_me_extend_valid(struct device *dev) } printk(BIOS_DEBUG, "\n"); -#if CONFIG(CHROMEOS) /* Save hash in NVS for the OS to verify */ - chromeos_set_me_hash(extend, count); -#endif + if (CONFIG(CHROMEOS)) + chromeos_set_me_hash(extend, count); return 0; } |