diff options
| -rw-r--r-- | src/soc/intel/xeon_sp/spr/Kconfig | 3 | ||||
| -rw-r--r-- | src/soc/intel/xeon_sp/spr/romstage.c | 4 |
2 files changed, 3 insertions, 4 deletions
diff --git a/src/soc/intel/xeon_sp/spr/Kconfig b/src/soc/intel/xeon_sp/spr/Kconfig index b84a8ff267..6fad812941 100644 --- a/src/soc/intel/xeon_sp/spr/Kconfig +++ b/src/soc/intel/xeon_sp/spr/Kconfig @@ -174,10 +174,9 @@ config ENABLE_RMT Enable Rank Margining Tool. This option is intended for debugging and validation and should normally be disabled. -config RMT_MEM_POR_FREQ +config MEM_POR_FREQ bool "Enforce Plan Of Record restrictions for DDR5 frequency and voltage" default n - depends on ENABLE_RMT help When RMT is enabled. Select this option to enforce Intel Plan Of Record(POR) restriction on DDR5 frequency & voltage settings. diff --git a/src/soc/intel/xeon_sp/spr/romstage.c b/src/soc/intel/xeon_sp/spr/romstage.c index b05c7e76fd..4d95a33365 100644 --- a/src/soc/intel/xeon_sp/spr/romstage.c +++ b/src/soc/intel/xeon_sp/spr/romstage.c @@ -241,9 +241,9 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) mupd->FspmConfig.serialDebugMsgLvl = 0x3; mupd->FspmConfig.AllowedSocketsInParallel = 0x1; mupd->FspmConfig.EnforcePopulationPor = 0x1; - if (CONFIG(RMT_MEM_POR_FREQ)) - mupd->FspmConfig.EnforceDdrMemoryFreqPor = 0x0; } + if (CONFIG(MEM_POR_FREQ)) + mupd->FspmConfig.EnforceDdrMemoryFreqPor = 0x0; /* SPR-FSP has no UPD to disable HDA, so do it manually here... */ if (!is_devfn_enabled(PCH_DEVFN_HDA)) |