diff options
| -rw-r--r-- | src/mainboard/google/brya/variants/uldren/Makefile.inc | 6 | ||||
| -rw-r--r-- | src/mainboard/google/brya/variants/uldren/gpio.c | 97 |
2 files changed, 103 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/uldren/Makefile.inc b/src/mainboard/google/brya/variants/uldren/Makefile.inc new file mode 100644 index 0000000000..6f46b7adc7 --- /dev/null +++ b/src/mainboard/google/brya/variants/uldren/Makefile.inc @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +bootblock-y += gpio.c + +romstage-y += gpio.c + +ramstage-y += gpio.c diff --git a/src/mainboard/google/brya/variants/uldren/gpio.c b/src/mainboard/google/brya/variants/uldren/gpio.c new file mode 100644 index 0000000000..9c427f64e7 --- /dev/null +++ b/src/mainboard/google/brya/variants/uldren/gpio.c @@ -0,0 +1,97 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <commonlib/helpers.h> +#include <soc/gpio.h> + +/* Pad configuration in ramstage */ +static const struct pad_config override_gpio_table[] = { + /* A8 : WWAN_RF_DISABLE_ODL */ + PAD_CFG_GPO(GPP_A8, 1, DEEP), + /* A20 : DDSP_HPD2 ==> NC */ + PAD_NC(GPP_A20, NONE), + /* B5 : I2C2_SDA ==> NC */ + PAD_NC(GPP_B5, NONE), + /* B6 : I2C2_SCL ==> NC */ + PAD_NC(GPP_B6, NONE), + /* B15 : HP_RST_ODL */ + PAD_CFG_GPO(GPP_B15, 1, DEEP), + /* D6 : SRCCLKREQ1# ==> WWAN_EN */ + PAD_CFG_GPO(GPP_D6, 1, DEEP), + /* D8 : SRCCLKREQ3# ==> NC */ + PAD_NC(GPP_D8, NONE), + /* D15 : ISH_UART0_RTS# ==> NC */ + PAD_NC(GPP_D15, NONE), + /* D16 : ISH_UART0_CTS# ==> NC */ + PAD_NC_LOCK(GPP_D16, NONE, LOCK_CONFIG), + /* D19 : I2S_MCLK1_OUT ==> NC */ + PAD_NC(GPP_D19, NONE), + /* E20 : DDP2_CTRLCLK ==> NC */ + PAD_NC(GPP_E20, NONE), + /* E21 : DDP2_CTRLDATA ==> NC */ + PAD_NC(GPP_E21, NONE), + /* F12 : WWAN_RST_L */ + PAD_CFG_GPO_LOCK(GPP_F12, 1, LOCK_CONFIG), + /* F13 : SOC_PEN_DETECT_R_ODL ==> NC*/ + PAD_NC(GPP_F13, NONE), + /* F15 : SOC_PEN_DETECT_ODL ==> NC*/ + PAD_NC_LOCK(GPP_F15, NONE, LOCK_CONFIG), + /* F18 : EC_IN_RW_OD ==> NC */ + PAD_NC(GPP_F18, NONE), + /* H3 : WLAN_PCIE_WAKE_ODL ==> NC */ + PAD_NC_LOCK(GPP_H3, NONE, LOCK_CONFIG), + /* H12 : UART0_RTS# ==> NC */ + PAD_NC(GPP_H12, NONE), + /* H13 : UART0_CTS# ==> NC */ + PAD_NC(GPP_H13, NONE), + /* H20 : WLAN_PERST_L ==> NC */ + PAD_NC(GPP_H20, NONE), + /* H22 : IMGCLKOUT3 ==> NC */ + PAD_NC(GPP_H22, NONE), +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* A13 : GPP_A13 ==> GSC_SOC_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), + /* B15 : HP_RST_ODL */ + PAD_CFG_GPO(GPP_B15, 0, DEEP), + /* D6 : SRCCLKREQ1# ==> WWAN_EN */ + PAD_CFG_GPO(GPP_D6, 1, DEEP), + /* E12 : THC0_SPI1_IO1 ==> SOC_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_E12, NONE, DEEP), + /* F12 : GSXDOUT ==> WWAN_RST_L */ + PAD_CFG_GPO(GPP_F12, 0, DEEP), + /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_F18, NONE, DEEP), + /* H4 : I2C0_SDA ==> SOC_I2C_GSC_SDA */ + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), + /* H5 : I2C0_SCL ==> SOC_I2C_GSC_SCL */ + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), + /* H10 : UART0_RXD ==> UART_SOC_RX_DBG_TX */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), + /* H11 : UART0_TXD ==> UART_SOC_TX_DBG_RX */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), +}; + +static const struct pad_config romstage_gpio_table[] = { +}; + +const struct pad_config *variant_gpio_override_table(size_t *num) +{ + *num = ARRAY_SIZE(override_gpio_table); + return override_gpio_table; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +const struct pad_config *variant_romstage_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(romstage_gpio_table); + return romstage_gpio_table; +} |