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-rw-r--r--src/northbridge/intel/haswell/haswell.h29
1 files changed, 17 insertions, 12 deletions
diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h
index f3f525d770..49e31a8e66 100644
--- a/src/northbridge/intel/haswell/haswell.h
+++ b/src/northbridge/intel/haswell/haswell.h
@@ -72,9 +72,6 @@
#define EPVC1RCTL 0x020 /* 32bit */
#define EPVC1RSTS 0x026 /* 16bit */
-#define EPVC1MTS 0x028 /* 32bit */
-#define EPVC1IST 0x038 /* 64bit */
-
#define EPESD 0x044 /* 32bit */
#define EPLE1D 0x050 /* 32bit */
@@ -82,8 +79,6 @@
#define EPLE2D 0x060 /* 32bit */
#define EPLE2A 0x068 /* 64bit */
-#define PORTARB 0x100 /* 256bit */
-
/*
* DMIBAR
*/
@@ -95,16 +90,30 @@
#define DMIVCECH 0x000 /* 32bit */
#define DMIPVCCAP1 0x004 /* 32bit */
#define DMIPVCCAP2 0x008 /* 32bit */
-
#define DMIPVCCCTL 0x00c /* 16bit */
#define DMIVC0RCAP 0x010 /* 32bit */
-#define DMIVC0RCTL0 0x014 /* 32bit */
+#define DMIVC0RCTL 0x014 /* 32bit */
#define DMIVC0RSTS 0x01a /* 16bit */
+#define VC0NP (1 << 1)
#define DMIVC1RCAP 0x01c /* 32bit */
#define DMIVC1RCTL 0x020 /* 32bit */
#define DMIVC1RSTS 0x026 /* 16bit */
+#define VC1NP (1 << 1)
+
+#define DMIVCPRCAP 0x028 /* 32bit */
+#define DMIVCPRCTL 0x02c /* 32bit */
+#define DMIVCPRSTS 0x032 /* 16bit */
+#define VCPNP (1 << 1)
+
+#define DMIVCMRCAP 0x034 /* 32bit */
+#define DMIVCMRCTL 0x038 /* 32bit */
+#define DMIVCMRSTS 0x03e /* 16bit */
+#define VCMNP (1 << 1)
+
+#define DMIRCLDECH 0x040 /* 32bit */
+#define DMIESD 0x044 /* 32bit */
#define DMILE1D 0x050 /* 32bit */
#define DMILE1A 0x058 /* 64bit */
@@ -116,9 +125,7 @@
#define DMILSTS 0x08a /* 16bit */
#define DMILCTL2 0x098 /* 16bit */
-
-#define DMICTL1 0x0f0 /* 32bit */
-#define DMICTL2 0x0fc /* 32bit */
+#define DMILSTS2 0x09c /* 16bit */
#define DMIUESTS 0x1c4 /* 32bit */
#define DMICESTS 0x1d0 /* 32bit */
@@ -130,8 +137,6 @@
#define DMI_AFE_PM_TMR 0xc28 /* 32bit */
-#define DMIDRCCFG 0xeb4 /* 32bit */
-
#ifndef __ASSEMBLER__
void intel_northbridge_haswell_finalize_smm(void);