diff options
| -rw-r--r-- | src/soc/intel/common/block/gpio/Kconfig | 10 | ||||
| -rw-r--r-- | src/soc/intel/common/block/include/intelblocks/gpio.h | 6 |
2 files changed, 15 insertions, 1 deletions
diff --git a/src/soc/intel/common/block/gpio/Kconfig b/src/soc/intel/common/block/gpio/Kconfig index de0546cd60..60a5967bde 100644 --- a/src/soc/intel/common/block/gpio/Kconfig +++ b/src/soc/intel/common/block/gpio/Kconfig @@ -63,4 +63,14 @@ config SOC_INTEL_COMMON_BLOCK_GPIO_PMODE_4BITS SoC user to select this config if Pad Mode (PMODE) width of PAD_CFG_DW0 regiser is 4 bits to support Native Function 1 to 15. +config SOC_INTEL_COMMON_BLOCK_GPIO_16BIT_CPU_PORTID + bool + default n + help + Enable support for 16-bit CPU Port IDs. + Intel SoCs (starting with Panther Lake) have extended the CPU Port ID field + to 16 bits. + Enable this option if your platform requires the GPIO driver to + accommodate this larger Port ID value. + endif diff --git a/src/soc/intel/common/block/include/intelblocks/gpio.h b/src/soc/intel/common/block/include/intelblocks/gpio.h index 8e60a1633f..39d17a199a 100644 --- a/src/soc/intel/common/block/include/intelblocks/gpio.h +++ b/src/soc/intel/common/block/include/intelblocks/gpio.h @@ -136,7 +136,11 @@ struct pad_community { uint8_t gpi_status_offset; /* specifies offset in struct gpi_status */ uint8_t port; /* PCR Port ID */ - uint8_t cpu_port; /* CPU Port ID */ +#if CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_16BIT_CPU_PORTID) + uint16_t cpu_port; /* Use 16-bit CPU Port ID */ +#else + uint8_t cpu_port; /* Use 8-bit CPU Port ID */ +#endif const struct reset_mapping *reset_map; /* PADRSTCFG logical to chipset mapping */ size_t num_reset_vals; |