diff options
| -rw-r--r-- | src/mainboard/getac/p470/smihandler.c | 1 | ||||
| -rw-r--r-- | src/southbridge/intel/bd82x6x/gpio.c | 96 | ||||
| -rw-r--r-- | src/southbridge/intel/bd82x6x/gpio.h | 177 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801gx/i82801gx.h | 10 | ||||
| -rw-r--r-- | src/southbridge/intel/ibexpeak/Kconfig | 1 | ||||
| -rw-r--r-- | src/southbridge/intel/ibexpeak/Makefile.inc | 2 | ||||
| -rw-r--r-- | src/southbridge/intel/ibexpeak/pch.h | 16 | ||||
| -rw-r--r-- | src/southbridge/intel/ibexpeak/smihandler.c | 1 |
8 files changed, 4 insertions, 300 deletions
diff --git a/src/mainboard/getac/p470/smihandler.c b/src/mainboard/getac/p470/smihandler.c index 0dbb4529a2..2d1a0cd8f5 100644 --- a/src/mainboard/getac/p470/smihandler.c +++ b/src/mainboard/getac/p470/smihandler.c @@ -19,6 +19,7 @@ #include <cpu/x86/smm.h> #include "southbridge/intel/i82801gx/i82801gx.h" #include "southbridge/intel/i82801gx/nvs.h" +#include <southbridge/intel/common/gpio.h> #include <ec/acpi/ec.h> #include "ec_oem.c" diff --git a/src/southbridge/intel/bd82x6x/gpio.c b/src/southbridge/intel/bd82x6x/gpio.c deleted file mode 100644 index 662415608a..0000000000 --- a/src/southbridge/intel/bd82x6x/gpio.c +++ /dev/null @@ -1,96 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <string.h> -#include <arch/io.h> - -#include "pch.h" -#include "gpio.h" - -#define MAX_GPIO_NUMBER 75 /* zero based */ - -void setup_pch_gpios(const struct pch_gpio_map *gpio) -{ - u16 gpiobase = pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffc; - - /* GPIO Set 1 */ - if (gpio->set1.level) - outl(*((u32*)gpio->set1.level), gpiobase + GP_LVL); - if (gpio->set1.mode) - outl(*((u32*)gpio->set1.mode), gpiobase + GPIO_USE_SEL); - if (gpio->set1.direction) - outl(*((u32*)gpio->set1.direction), gpiobase + GP_IO_SEL); - if (gpio->set1.reset) - outl(*((u32*)gpio->set1.reset), gpiobase + GP_RST_SEL1); - if (gpio->set1.invert) - outl(*((u32*)gpio->set1.invert), gpiobase + GPI_INV); - if (gpio->set1.blink) - outl(*((u32*)gpio->set1.blink), gpiobase + GPO_BLINK); - - /* GPIO Set 2 */ - if (gpio->set2.level) - outl(*((u32*)gpio->set2.level), gpiobase + GP_LVL2); - if (gpio->set2.mode) - outl(*((u32*)gpio->set2.mode), gpiobase + GPIO_USE_SEL2); - if (gpio->set2.direction) - outl(*((u32*)gpio->set2.direction), gpiobase + GP_IO_SEL2); - if (gpio->set2.reset) - outl(*((u32*)gpio->set2.reset), gpiobase + GP_RST_SEL2); - - /* GPIO Set 3 */ - if (gpio->set3.level) - outl(*((u32*)gpio->set3.level), gpiobase + GP_LVL3); - if (gpio->set3.mode) - outl(*((u32*)gpio->set3.mode), gpiobase + GPIO_USE_SEL3); - if (gpio->set3.direction) - outl(*((u32*)gpio->set3.direction), gpiobase + GP_IO_SEL3); - if (gpio->set3.reset) - outl(*((u32*)gpio->set3.reset), gpiobase + GP_RST_SEL3); -} - -int get_gpio(int gpio_num) -{ - static const int gpio_reg_offsets[] = {0xc, 0x38, 0x48}; - u16 gpio_base = pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffc; - int index, bit; - - if (gpio_num > MAX_GPIO_NUMBER) - return 0; /* Just ignore wrong gpio numbers. */ - - index = gpio_num / 32; - bit = gpio_num % 32; - - return (inl(gpio_base + gpio_reg_offsets[index]) >> bit) & 1; -} - -/* - * get a number comprised of multiple GPIO values. gpio_num_array points to - * the array of gpio pin numbers to scan, terminated by -1. - */ -unsigned get_gpios(const int *gpio_num_array) -{ - int gpio; - unsigned bitmask = 1; - unsigned vector = 0; - - while (bitmask && - ((gpio = *gpio_num_array++) != -1)) { - if (get_gpio(gpio)) - vector |= bitmask; - bitmask <<= 1; - } - return vector; -} diff --git a/src/southbridge/intel/bd82x6x/gpio.h b/src/southbridge/intel/bd82x6x/gpio.h deleted file mode 100644 index 28b66b437e..0000000000 --- a/src/southbridge/intel/bd82x6x/gpio.h +++ /dev/null @@ -1,177 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef INTEL_BD82X6X_GPIO_H -#define INTEL_BD82X6X_GPIO_H - -#include <stdint.h> - -/* ICH7 GPIOBASE */ -#define GPIO_USE_SEL 0x00 -#define GP_IO_SEL 0x04 -#define GP_LVL 0x0c -#define GPO_BLINK 0x18 -#define GPI_INV 0x2c -#define GPIO_USE_SEL2 0x30 -#define GP_IO_SEL2 0x34 -#define GP_LVL2 0x38 -#define GPIO_USE_SEL3 0x40 -#define GP_IO_SEL3 0x44 -#define GP_LVL3 0x48 -#define GP_RST_SEL1 0x60 -#define GP_RST_SEL2 0x64 -#define GP_RST_SEL3 0x68 - -#define GPIO_MODE_NATIVE 0 -#define GPIO_MODE_GPIO 1 -#define GPIO_MODE_NONE 1 - -#define GPIO_DIR_OUTPUT 0 -#define GPIO_DIR_INPUT 1 - -#define GPIO_NO_INVERT 0 -#define GPIO_INVERT 1 - -#define GPIO_LEVEL_LOW 0 -#define GPIO_LEVEL_HIGH 1 - -#define GPIO_NO_BLINK 0 -#define GPIO_BLINK 1 - -#define GPIO_RESET_PWROK 0 -#define GPIO_RESET_RSMRST 1 - -struct pch_gpio_set1 { - u32 gpio0 : 1; - u32 gpio1 : 1; - u32 gpio2 : 1; - u32 gpio3 : 1; - u32 gpio4 : 1; - u32 gpio5 : 1; - u32 gpio6 : 1; - u32 gpio7 : 1; - u32 gpio8 : 1; - u32 gpio9 : 1; - u32 gpio10 : 1; - u32 gpio11 : 1; - u32 gpio12 : 1; - u32 gpio13 : 1; - u32 gpio14 : 1; - u32 gpio15 : 1; - u32 gpio16 : 1; - u32 gpio17 : 1; - u32 gpio18 : 1; - u32 gpio19 : 1; - u32 gpio20 : 1; - u32 gpio21 : 1; - u32 gpio22 : 1; - u32 gpio23 : 1; - u32 gpio24 : 1; - u32 gpio25 : 1; - u32 gpio26 : 1; - u32 gpio27 : 1; - u32 gpio28 : 1; - u32 gpio29 : 1; - u32 gpio30 : 1; - u32 gpio31 : 1; -} __attribute__ ((packed)); - -struct pch_gpio_set2 { - u32 gpio32 : 1; - u32 gpio33 : 1; - u32 gpio34 : 1; - u32 gpio35 : 1; - u32 gpio36 : 1; - u32 gpio37 : 1; - u32 gpio38 : 1; - u32 gpio39 : 1; - u32 gpio40 : 1; - u32 gpio41 : 1; - u32 gpio42 : 1; - u32 gpio43 : 1; - u32 gpio44 : 1; - u32 gpio45 : 1; - u32 gpio46 : 1; - u32 gpio47 : 1; - u32 gpio48 : 1; - u32 gpio49 : 1; - u32 gpio50 : 1; - u32 gpio51 : 1; - u32 gpio52 : 1; - u32 gpio53 : 1; - u32 gpio54 : 1; - u32 gpio55 : 1; - u32 gpio56 : 1; - u32 gpio57 : 1; - u32 gpio58 : 1; - u32 gpio59 : 1; - u32 gpio60 : 1; - u32 gpio61 : 1; - u32 gpio62 : 1; - u32 gpio63 : 1; -} __attribute__ ((packed)); - -struct pch_gpio_set3 { - u32 gpio64 : 1; - u32 gpio65 : 1; - u32 gpio66 : 1; - u32 gpio67 : 1; - u32 gpio68 : 1; - u32 gpio69 : 1; - u32 gpio70 : 1; - u32 gpio71 : 1; - u32 gpio72 : 1; - u32 gpio73 : 1; - u32 gpio74 : 1; - u32 gpio75 : 1; -} __attribute__ ((packed)); - -struct pch_gpio_map { - struct { - const struct pch_gpio_set1 *mode; - const struct pch_gpio_set1 *direction; - const struct pch_gpio_set1 *level; - const struct pch_gpio_set1 *reset; - const struct pch_gpio_set1 *invert; - const struct pch_gpio_set1 *blink; - } set1; - struct { - const struct pch_gpio_set2 *mode; - const struct pch_gpio_set2 *direction; - const struct pch_gpio_set2 *level; - const struct pch_gpio_set2 *reset; - } set2; - struct { - const struct pch_gpio_set3 *mode; - const struct pch_gpio_set3 *direction; - const struct pch_gpio_set3 *level; - const struct pch_gpio_set3 *reset; - } set3; -}; - -extern const struct pch_gpio_map mainboard_gpio_map; - -/* Configure GPIOs with mainboard provided settings */ -void setup_pch_gpios(const struct pch_gpio_map *gpio); - -/* get GPIO pin value */ -int get_gpio(int gpio_num); -/* - * get a number comprised of multiple GPIO values. gpio_num_array points to - * the array of gpio pin numbers to scan, terminated by -1. - */ -unsigned get_gpios(const int *gpio_num_array); - -#endif diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index 35297c764a..17b7026733 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -302,16 +302,6 @@ int southbridge_detect_s3_resume(void); #define FD_SATA (1 << 2) #define FD_PATA (1 << 1) -/* ICH7 GPIOBASE */ -#define GPIO_USE_SEL 0x00 -#define GP_IO_SEL 0x04 -#define GP_LVL 0x0c -#define GPO_BLINK 0x18 -#define GPI_INV 0x2c -#define GPIO_USE_SEL2 0x30 -#define GP_IO_SEL2 0x34 -#define GP_LVL2 0x38 - /* ICH7 PMBASE */ #define PM1_STS 0x00 #define WAK_STS (1 << 15) diff --git a/src/southbridge/intel/ibexpeak/Kconfig b/src/southbridge/intel/ibexpeak/Kconfig index ffc0a1692d..f12068c707 100644 --- a/src/southbridge/intel/ibexpeak/Kconfig +++ b/src/southbridge/intel/ibexpeak/Kconfig @@ -33,6 +33,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy select COMMON_FADT select ACPI_SATA_GENERATOR select HAVE_INTEL_FIRMWARE + select SOUTHBRIDGE_INTEL_COMMON_GPIO config EHCI_BAR hex diff --git a/src/southbridge/intel/ibexpeak/Makefile.inc b/src/southbridge/intel/ibexpeak/Makefile.inc index 2987ea9df7..41d3afbecd 100644 --- a/src/southbridge/intel/ibexpeak/Makefile.inc +++ b/src/southbridge/intel/ibexpeak/Makefile.inc @@ -42,7 +42,7 @@ smm-$(CONFIG_SPI_FLASH_SMM) += ../common/spi.c ramstage-y += smi.c smm-y += smihandler.c me.c ../bd82x6x/me_8.x.c ../bd82x6x/finalize.c ../bd82x6x/pch.c -romstage-y += ../bd82x6x/early_usb.c early_smbus.c ../bd82x6x/early_me.c ../bd82x6x/me_status.c ../bd82x6x/gpio.c early_thermal.c +romstage-y += ../bd82x6x/early_usb.c early_smbus.c ../bd82x6x/early_me.c ../bd82x6x/me_status.c ../common/gpio.c early_thermal.c romstage-y += ../bd82x6x/reset.c romstage-y += ../bd82x6x/early_rcba.c romstage-$(CONFIG_SOUTHBRIDGE_INTEL_BD82X6X) += ../bd82x6x/early_spi.c diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h index 057214332d..07127fafbf 100644 --- a/src/southbridge/intel/ibexpeak/pch.h +++ b/src/southbridge/intel/ibexpeak/pch.h @@ -432,22 +432,6 @@ void southbridge_configure_default_intmap(void); #define PCH_DISABLE_MEI1 (1 << 1) #define PCH_ENABLE_DBDF (1 << 0) -/* ICH7 GPIOBASE */ -#define GPIO_USE_SEL 0x00 -#define GP_IO_SEL 0x04 -#define GP_LVL 0x0c -#define GPO_BLINK 0x18 -#define GPI_INV 0x2c -#define GPIO_USE_SEL2 0x30 -#define GP_IO_SEL2 0x34 -#define GP_LVL2 0x38 -#define GPIO_USE_SEL3 0x40 -#define GP_IO_SEL3 0x44 -#define GP_LVL3 0x48 -#define GP_RST_SEL1 0x60 -#define GP_RST_SEL2 0x64 -#define GP_RST_SEL3 0x68 - /* ICH7 PMBASE */ #define PM1_STS 0x00 #define WAK_STS (1 << 15) diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c index fb9693036f..319f9946c8 100644 --- a/src/southbridge/intel/ibexpeak/smihandler.c +++ b/src/southbridge/intel/ibexpeak/smihandler.c @@ -32,6 +32,7 @@ * 2. we don't need to worry about how we leave 0xcf8/0xcfc behind */ #include "northbridge/intel/nehalem/nehalem.h" +#include <southbridge/intel/common/gpio.h> #include <arch/pci_mmio_cfg.h> /* While we read PMBASE dynamically in case it changed, let's |