diff options
| -rw-r--r-- | src/southbridge/via/k8t890/k8t890_bridge.c | 8 | ||||
| -rw-r--r-- | src/southbridge/via/k8t890/k8t890_dram.c | 23 | ||||
| -rw-r--r-- | src/southbridge/via/k8t890/k8t890_host_ctrl.c | 4 |
3 files changed, 22 insertions, 13 deletions
diff --git a/src/southbridge/via/k8t890/k8t890_bridge.c b/src/southbridge/via/k8t890/k8t890_bridge.c index be1ba721ef..44347127f6 100644 --- a/src/southbridge/via/k8t890/k8t890_bridge.c +++ b/src/southbridge/via/k8t890/k8t890_bridge.c @@ -24,8 +24,8 @@ static void bridge_enable(struct device *dev) { + u8 tmp; print_debug("B188 device dump\n"); - /* VIA recommends this, sorry no known info. */ writeback(dev, 0x40, 0x91); @@ -44,6 +44,12 @@ static void bridge_enable(struct device *dev) writeback(dev, 0x3e, 0x16); dump_south(dev); + + /* disable I/O and memory decode, or it freezes PCI bus during BAR sizing */ + tmp = pci_read_config8(dev, PCI_COMMAND); + tmp &= ~0x3; + pci_write_config8(dev, PCI_COMMAND, tmp); + } static const struct device_operations bridge_ops = { diff --git a/src/southbridge/via/k8t890/k8t890_dram.c b/src/southbridge/via/k8t890/k8t890_dram.c index 00e5fa5f24..1c60a78a13 100644 --- a/src/southbridge/via/k8t890/k8t890_dram.c +++ b/src/southbridge/via/k8t890/k8t890_dram.c @@ -63,6 +63,15 @@ static void dram_enable(struct device *dev) /* The Address Next to the Last Valid DRAM Address */ pci_write_config16(dev, 0x88, (msr.lo >> 24) | reg); + +} + +static void dram_enable_k8m890(struct device *dev) +{ + dram_enable(dev); + + /* enable VGA, so the bridges gets VGA_EN and resources are set */ + pci_write_config8(dev, 0xa1, 0x80); } static struct resource *resmax; @@ -113,17 +122,11 @@ static void dram_init_fb(struct device *dev) printk_debug("VIA FB proposed base: %llx\n", proposed_base); - /* enable UMA but no FB */ + /* Step 1: enable UMA but no FB */ pci_write_config8(dev, 0xa1, 0x80); - /* 27:21 goes to 7:1, 0 is enable CPU access */ - tmp = (proposed_base >> 20) | 0x1; - pci_write_config8(dev, 0xa0, tmp); - - /* 31:28 goes to 3:0 */ - tmp = ((proposed_base >> 28) & 0xf); - tmp = ((log2(K8M890_FBSIZEMB) - 2) << 4); - tmp |= 0x80; + /* Step 2: enough is just the FB size, the CPU accessible address is not needed */ + tmp = ((log2(K8M890_FBSIZEMB) - 2) << 4) | 0x80; pci_write_config8(dev, 0xa1, tmp); /* TODO K8 needs some UMA fine tuning too maybe call some generic routine here? */ @@ -141,7 +144,7 @@ static const struct device_operations dram_ops_m = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .enable = dram_enable, + .enable = dram_enable_k8m890, .init = dram_init_fb, .ops_pci = 0, }; diff --git a/src/southbridge/via/k8t890/k8t890_host_ctrl.c b/src/southbridge/via/k8t890/k8t890_host_ctrl.c index f2bc88ad65..faa498e8b0 100644 --- a/src/southbridge/via/k8t890/k8t890_host_ctrl.c +++ b/src/southbridge/via/k8t890/k8t890_host_ctrl.c @@ -105,8 +105,8 @@ static void host_ctrl_enable_k8m890(struct device *dev) { /* Arbitration control */ pci_write_config8(dev, 0xa5, 0x3c); - /* Arbitration control 2 */ - pci_write_config8(dev, 0xa6, 0x82); + /* Arbitration control 2, Enable C2NOW delay to PSTATECTL */ + pci_write_config8(dev, 0xa6, 0x83); } |