diff options
| -rw-r--r-- | src/soc/intel/alderlake/Kconfig | 6 | ||||
| -rw-r--r-- | src/soc/intel/alderlake/acpi/tcss.asl | 8 | ||||
| -rw-r--r-- | src/soc/intel/alderlake/acpi/tcss_dma.asl | 22 | ||||
| -rw-r--r-- | src/soc/intel/alderlake/acpi/tcss_pcierp.asl | 20 | ||||
| -rw-r--r-- | src/soc/intel/alderlake/acpi/tcss_xhci.asl | 6 |
5 files changed, 61 insertions, 1 deletions
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index e6151313ae..0b5328103a 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -292,6 +292,12 @@ config SOC_INTEL_I2C_DEV_MAX int default 8 +config SOC_INTEL_ALDERLAKE_S3 + bool + default n + help + Select if using S3 instead of S0ix to disable D3Cold. + config SOC_INTEL_UART_DEV_MAX int default 7 diff --git a/src/soc/intel/alderlake/acpi/tcss.asl b/src/soc/intel/alderlake/acpi/tcss.asl index c8cea84dd8..66aa908709 100644 --- a/src/soc/intel/alderlake/acpi/tcss.asl +++ b/src/soc/intel/alderlake/acpi/tcss.asl @@ -41,6 +41,12 @@ Scope (\_SB) { +#if !CONFIG(SOC_INTEL_ALDERLAKE_S3) + Name (S0IX, 0) +#else + Name (S0IX, 1) +#endif + /* Device base address */ Method (BASE, 1) { @@ -573,6 +579,7 @@ Scope (\_SB.PCI0) } } +#if !CONFIG(SOC_INTEL_ALDERLAKE_S3) Method (TCON, 0) { /* Reset IOM D3 cold bit if it is in D3 cold now. */ @@ -643,6 +650,7 @@ Scope (\_SB.PCI0) STAT = 0 } } +#endif /* * TCSS xHCI device diff --git a/src/soc/intel/alderlake/acpi/tcss_dma.asl b/src/soc/intel/alderlake/acpi/tcss_dma.asl index 0b5e03f913..989fbd5c96 100644 --- a/src/soc/intel/alderlake/acpi/tcss_dma.asl +++ b/src/soc/intel/alderlake/acpi/tcss_dma.asl @@ -28,25 +28,45 @@ Name (STAT, 0x1) /* Variable to save power state 1 - D0, 0 - D3C */ Method (_S0W, 0x0) { - Return (0x4) +#if !CONFIG(SOC_INTEL_ALDERLAKE_S3) + Return (0x04) +#else + Return (0x03) +#endif } Method (_PR0) { +#if !CONFIG(SOC_INTEL_ALDERLAKE_S3) If (DUID == 0) { Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 }) } Else { Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT1 }) } +#else + If (DUID == 0) { + Return (Package() { \_SB.PCI0.TBT0 }) + } Else { + Return (Package() { \_SB.PCI0.TBT1 }) + } +#endif } Method (_PR3) { +#if !CONFIG(SOC_INTEL_ALDERLAKE_S3) If (DUID == 0) { Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 }) } Else { Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT1 }) } +#else + If (DUID == 0) { + Return (Package() { \_SB.PCI0.TBT0 }) + } Else { + Return (Package() { \_SB.PCI0.TBT1 }) + } +#endif } /* diff --git a/src/soc/intel/alderlake/acpi/tcss_pcierp.asl b/src/soc/intel/alderlake/acpi/tcss_pcierp.asl index 799c0ce94f..dee265c3a3 100644 --- a/src/soc/intel/alderlake/acpi/tcss_pcierp.asl +++ b/src/soc/intel/alderlake/acpi/tcss_pcierp.asl @@ -267,25 +267,45 @@ Method (_PS3, 0, Serialized) Method (_S0W, 0x0, NotSerialized) { +#if !CONFIG(SOC_INTEL_ALDERLAKE_S3) Return (0x4) +#else + Return (0x3) +#endif } Method (_PR0) { +#if !CONFIG(SOC_INTEL_ALDERLAKE_S3) If ((TUID == 0) || (TUID == 1)) { Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 }) } Else { Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT1 }) } +#else + If ((TUID == 0) || (TUID == 1)) { + Return (Package() { \_SB.PCI0.TBT0 }) + } Else { + Return (Package() { \_SB.PCI0.TBT1 }) + } +#endif } Method (_PR3) { +#if !CONFIG(SOC_INTEL_ALDERLAKE_S3) If ((TUID == 0) || (TUID == 1)) { Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 }) } Else { Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT1 }) } +#else + If ((TUID == 0) || (TUID == 1)) { + Return (Package() { \_SB.PCI0.TBT0 }) + } Else { + Return (Package() { \_SB.PCI0.TBT1 }) + } +#endif } /* diff --git a/src/soc/intel/alderlake/acpi/tcss_xhci.asl b/src/soc/intel/alderlake/acpi/tcss_xhci.asl index acbeb30c13..b3fe653d26 100644 --- a/src/soc/intel/alderlake/acpi/tcss_xhci.asl +++ b/src/soc/intel/alderlake/acpi/tcss_xhci.asl @@ -30,7 +30,11 @@ Method (_PS3, 0, Serialized) Method (_S0W, 0x0, NotSerialized) { +#if !CONFIG(SOC_INTEL_ALDERLAKE_S3) Return (0x4) +#else + Return (0x3) +#endif } /* @@ -39,6 +43,7 @@ Method (_S0W, 0x0, NotSerialized) */ Name (SD3C, 0) +#if !CONFIG(SOC_INTEL_ALDERLAKE_S3) Method (_PR0) { Return (Package () { \_SB.PCI0.D3C }) @@ -48,6 +53,7 @@ Method (_PR3) { Return (Package () { \_SB.PCI0.D3C }) } +#endif /* * XHCI controller _DSM method |