diff options
| -rw-r--r-- | src/arch/x86/car.ld | 6 | ||||
| -rw-r--r-- | src/drivers/intel/fsp2_0/Kconfig | 11 | ||||
| -rw-r--r-- | src/drivers/intel/fsp2_0/memory_init.c | 8 | ||||
| -rw-r--r-- | src/soc/intel/xeon_sp/cpx/Kconfig | 1 | ||||
| -rw-r--r-- | src/soc/intel/xeon_sp/spr/Kconfig | 1 |
5 files changed, 25 insertions, 2 deletions
diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld index 17e6eea06d..8e1af15df3 100644 --- a/src/arch/x86/car.ld +++ b/src/arch/x86/car.ld @@ -9,6 +9,10 @@ .car.data . (NOLOAD) : { _car_region_start = . ; . += CONFIG_FSP_M_RC_HEAP_SIZE; +#if CONFIG(FSP_SPEC_VIOLATION_XEON_SP_HEAP_WORKAROUND) + REGION(fspm_heap, ., CONFIG_FSP_TEMP_RAM_SIZE, 16) +#endif + #if CONFIG(PAGING_IN_CACHE_AS_RAM) /* Page table pre-allocation. CONFIG_DCACHE_RAM_BASE should be 4KiB * aligned when using this option. */ @@ -107,7 +111,7 @@ _car_region_end = . + CONFIG_DCACHE_RAM_SIZE - (. - _car_region_start) . = _car_region_start; .car.fspm_rc_heap . (NOLOAD) : { -. += CONFIG_FSP_M_RC_HEAP_SIZE; + . += CONFIG_FSP_M_RC_HEAP_SIZE; } . = _car_region_end; diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index e27249ff3c..274c3e5f24 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -221,6 +221,17 @@ config FSP_USES_CB_STACK without reinitializing stack pointer. This feature is supported Icelake onwards. +config FSP_SPEC_VIOLATION_XEON_SP_HEAP_WORKAROUND + bool + help + Starting with Intel CPX there is a bug in there reference code during + the pipe init. This code synchronises the CAR between sockets in FSP-M. + This code implicitly assumes that the FSP heap is right above the + RC heap, where both of them are located at the bottom part of CAR. + Select this to have an explicit handling of the FSP StackBase to work + around this issue. This is needed on multi-socket Xeon-SP systems. + This will place the FSP heap right above the FSP-M RC heap. + config FSP_TEMP_RAM_SIZE hex help diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index f5de5c345d..c096e86dfe 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -170,7 +170,13 @@ static enum cb_err fsp_fill_common_arch_params(FSPM_ARCH_UPD *arch_upd, [FSP_BOOT_IN_RECOVERY_MODE] = "boot in recovery mode", }; - if (CONFIG(FSP_USES_CB_STACK) || !ENV_CACHE_AS_RAM) { + if (CONFIG(FSP_USES_CB_STACK) && ENV_RAMINIT + && CONFIG(FSP_SPEC_VIOLATION_XEON_SP_HEAP_WORKAROUND)) { + extern char _fspm_heap[]; + extern char _efspm_heap[]; + arch_upd->StackBase = (uintptr_t)_fspm_heap; + arch_upd->StackSize = (size_t)(_efspm_heap - _fspm_heap); + } else if (CONFIG(FSP_USES_CB_STACK) || !ENV_CACHE_AS_RAM) { arch_upd->StackBase = (uintptr_t)temp_ram; arch_upd->StackSize = sizeof(temp_ram); } else if (setup_fsp_stack_frame(arch_upd, memmap)) { diff --git a/src/soc/intel/xeon_sp/cpx/Kconfig b/src/soc/intel/xeon_sp/cpx/Kconfig index ac166c3038..b9d63d3ad2 100644 --- a/src/soc/intel/xeon_sp/cpx/Kconfig +++ b/src/soc/intel/xeon_sp/cpx/Kconfig @@ -7,6 +7,7 @@ config SOC_INTEL_COOPERLAKE_SP select CACHE_MRC_SETTINGS select NO_FSP_TEMP_RAM_EXIT select HAVE_INTEL_FSP_REPO + select FSP_SPEC_VIOLATION_XEON_SP_HEAP_WORKAROUND help Intel Cooper Lake-SP support diff --git a/src/soc/intel/xeon_sp/spr/Kconfig b/src/soc/intel/xeon_sp/spr/Kconfig index bb88becaa7..ace5c07042 100644 --- a/src/soc/intel/xeon_sp/spr/Kconfig +++ b/src/soc/intel/xeon_sp/spr/Kconfig @@ -13,6 +13,7 @@ config SOC_INTEL_SAPPHIRERAPIDS_SP select SOC_INTEL_CSE_SERVER_SKU select XEON_SP_COMMON_BASE select HAVE_IOAT_DOMAINS + select FSP_SPEC_VIOLATION_XEON_SP_HEAP_WORKAROUND help Intel Sapphire Rapids-SP support |