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-rw-r--r--src/drivers/intel/ptt/ptt.c12
-rw-r--r--src/security/intel/txt/txt_register.h5
2 files changed, 17 insertions, 0 deletions
diff --git a/src/drivers/intel/ptt/ptt.c b/src/drivers/intel/ptt/ptt.c
index 67ed0eebb7..5b0918bada 100644
--- a/src/drivers/intel/ptt/ptt.c
+++ b/src/drivers/intel/ptt/ptt.c
@@ -1,8 +1,11 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <arch/mmio.h>
#include <soc/pci_devs.h>
#include <device/pci_ops.h>
#include <console/console.h>
+#include <security/intel/txt/txt_register.h>
+#include <stdint.h>
#include "ptt.h"
@@ -27,6 +30,7 @@ static uint32_t read_register(int reg_addr)
*/
bool ptt_active(void)
{
+ uint32_t sts_ftif;
uint32_t fwsts4 = read_register(PCI_ME_HFSTS4);
if (fwsts4 == 0xFFFFFFFF)
@@ -34,6 +38,14 @@ bool ptt_active(void)
if ((fwsts4 & PTT_ENABLE) == 0) {
printk(BIOS_DEBUG, "Intel ME Establishment bit not valid.\n");
+ sts_ftif = read32p(TXT_STS_FTIF);
+
+ if (sts_ftif != 0 && sts_ftif != UINT32_MAX) {
+ if ((sts_ftif & TXT_PTT_PRESENT) == TXT_PTT_PRESENT) {
+ printk(BIOS_DEBUG, "TXT_STS_FTIF: PTT present and active\n");
+ return true;
+ }
+ }
return false;
}
diff --git a/src/security/intel/txt/txt_register.h b/src/security/intel/txt/txt_register.h
index 2137715edb..95f2a680d9 100644
--- a/src/security/intel/txt/txt_register.h
+++ b/src/security/intel/txt/txt_register.h
@@ -95,6 +95,11 @@
#define TXT_ACM_KEY_HASH (TXT_BASE + 0x400)
#define TXT_ACM_KEY_HASH_LEN 0x4
+#define TXT_STS_FTIF (TXT_BASE + 0x800)
+#define TXT_LPC_TPM_PRESENT 0x10000 /* Location of TPM: 001b - LPC TPM */
+#define TXT_SPI_TPM_PRESENT 0x50000 /* Location of TPM: 101b - SPI TPM */
+#define TXT_PTT_PRESENT 0x70000 /* Location of TPM: 111b - PTT present and active */
+
#define TXT_E2STS (TXT_BASE + 0x8f0)
#define TXT_E2STS_SECRET_STS (1ull << 1)