diff options
| -rw-r--r-- | src/soc/intel/alderlake/acpi/tcss.asl | 2 | ||||
| -rw-r--r-- | src/soc/intel/alderlake/include/soc/tcss.h | 20 | ||||
| -rw-r--r-- | src/soc/intel/common/block/include/intelblocks/tcss.h | 22 | ||||
| -rw-r--r-- | src/soc/intel/meteorlake/acpi/tcss.asl | 2 | ||||
| -rw-r--r-- | src/soc/intel/meteorlake/include/soc/tcss.h | 20 | ||||
| -rw-r--r-- | src/soc/intel/tigerlake/acpi/tcss.asl | 2 | ||||
| -rw-r--r-- | src/soc/intel/tigerlake/include/soc/tcss.h | 20 |
7 files changed, 25 insertions, 63 deletions
diff --git a/src/soc/intel/alderlake/acpi/tcss.asl b/src/soc/intel/alderlake/acpi/tcss.asl index 0890e4048c..826c60740a 100644 --- a/src/soc/intel/alderlake/acpi/tcss.asl +++ b/src/soc/intel/alderlake/acpi/tcss.asl @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ +#include <intelblocks/tcss.h> #include <soc/iomap.h> -#include <soc/tcss.h> /* * Type C Subsystem(TCSS) topology provides Runtime D3 support for USB host controller(xHCI), diff --git a/src/soc/intel/alderlake/include/soc/tcss.h b/src/soc/intel/alderlake/include/soc/tcss.h index 05baf5d534..014e3076e6 100644 --- a/src/soc/intel/alderlake/include/soc/tcss.h +++ b/src/soc/intel/alderlake/include/soc/tcss.h @@ -13,24 +13,4 @@ #define IOM_AUX_BIAS_CTRL_PULLDOWN_OFFSET_0 0x1088 #define IOM_AUX_BIAS_CTRL_PULLDOWN_OFFSET(x) (IOM_AUX_BIAS_CTRL_PULLDOWN_OFFSET_0 + (x) * 4) -/* - * The PCI-SIG engineering change requirement provides the ACPI additions for firmware latency - * optimization. Both of FW_RESET_TIME and FW_D3HOT_TO_D0_TIME are applicable to the upstream - * port of the USB4/TBT topology. - */ -/* Number of microseconds to wait after a conventional reset */ -#define FW_RESET_TIME 50000 - -/* Number of microseconds to wait after data link layer active report */ -#define FW_DL_UP_TIME 1 - -/* Number of microseconds to wait after a function level reset */ -#define FW_FLR_RESET_TIME 1 - -/* Number of microseconds to wait from D3 hot to D0 transition */ -#define FW_D3HOT_TO_D0_TIME 50000 - -/* Number of microseconds to wait after setting the VF enable bit */ -#define FW_VF_ENABLE_TIME 1 - #endif /* _SOC_TCSS_H_ */ diff --git a/src/soc/intel/common/block/include/intelblocks/tcss.h b/src/soc/intel/common/block/include/intelblocks/tcss.h index 12400d8c5a..a3fec18086 100644 --- a/src/soc/intel/common/block/include/intelblocks/tcss.h +++ b/src/soc/intel/common/block/include/intelblocks/tcss.h @@ -4,6 +4,7 @@ #define _TCSS_H_ #include <intelblocks/gpio.h> +#if !defined(__ACPI__) #include <device/usbc_mux.h> /* PMC IPC related offsets and commands */ @@ -165,5 +166,26 @@ const struct tcss_port_map *tcss_get_port_info(size_t *num_ports); /* Method to validate the Thunderbolt authentication */ bool tcss_valid_tbt_auth(void); bool ioe_tcss_valid_tbt_auth(void); +#endif /* !defined(__ACPI__) */ + +/* + * The PCI-SIG engineering change requirement provides the ACPI additions for firmware latency + * optimization. Both of FW_RESET_TIME and FW_D3HOT_TO_D0_TIME are applicable to the upstream + * port of the USB4/TBT topology. + */ +/* Number of microseconds to wait after a conventional reset */ +#define FW_RESET_TIME 50000 + +/* Number of microseconds to wait after data link layer active report */ +#define FW_DL_UP_TIME 1 + +/* Number of microseconds to wait after a function level reset */ +#define FW_FLR_RESET_TIME 1 + +/* Number of microseconds to wait from D3 hot to D0 transition */ +#define FW_D3HOT_TO_D0_TIME 50000 + +/* Number of microseconds to wait after setting the VF enable bit */ +#define FW_VF_ENABLE_TIME 1 #endif /* _TCSS_H_ */ diff --git a/src/soc/intel/meteorlake/acpi/tcss.asl b/src/soc/intel/meteorlake/acpi/tcss.asl index cd964c4594..6635d085b4 100644 --- a/src/soc/intel/meteorlake/acpi/tcss.asl +++ b/src/soc/intel/meteorlake/acpi/tcss.asl @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ +#include <intelblocks/tcss.h> #include <soc/iomap.h> -#include <soc/tcss.h> /* * Type C Subsystem(TCSS) topology provides Runtime D3 support for USB host controller(xHCI), diff --git a/src/soc/intel/meteorlake/include/soc/tcss.h b/src/soc/intel/meteorlake/include/soc/tcss.h index 439606c6af..014e3076e6 100644 --- a/src/soc/intel/meteorlake/include/soc/tcss.h +++ b/src/soc/intel/meteorlake/include/soc/tcss.h @@ -13,24 +13,4 @@ #define IOM_AUX_BIAS_CTRL_PULLDOWN_OFFSET_0 0x1088 #define IOM_AUX_BIAS_CTRL_PULLDOWN_OFFSET(x) (IOM_AUX_BIAS_CTRL_PULLDOWN_OFFSET_0 + (x) * 4) -/* - * The PCI-SIG engineering change requirement provides the ACPI additions for firmware latency - * optimization. Both of FW_RESET_TIME and FW_D3HOT_TO_D0_TIME are applicable to the upstream - * port of the USB4/TBT topology. - */ -/* Number of microseconds to wait after a conventional reset */ -#define FW_RESET_TIME 50000 - -/* Number of microseconds to wait after data link layer active report */ -#define FW_DL_UP_TIME 1 - -/* Number of microseconds to wait after a function level reset */ -#define FW_FLR_RESET_TIME 1 - -/* Number of microseconds to wait from D3 hot to D0 transition */ -#define FW_D3HOT_TO_D0_TIME 50000 - -/* Number of microseconds to wait after setting the VF enable bit */ -#define FW_VF_ENABLE_TIME 1 - #endif /* _SOC_TCSS_H_ */ diff --git a/src/soc/intel/tigerlake/acpi/tcss.asl b/src/soc/intel/tigerlake/acpi/tcss.asl index 0606d20a01..b24a9e6464 100644 --- a/src/soc/intel/tigerlake/acpi/tcss.asl +++ b/src/soc/intel/tigerlake/acpi/tcss.asl @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ +#include <intelblocks/tcss.h> #include <soc/iomap.h> -#include <soc/tcss.h> /* * Type C Subsystem(TCSS) topology provides Runtime D3 support for USB host controller(xHCI), diff --git a/src/soc/intel/tigerlake/include/soc/tcss.h b/src/soc/intel/tigerlake/include/soc/tcss.h index 05baf5d534..014e3076e6 100644 --- a/src/soc/intel/tigerlake/include/soc/tcss.h +++ b/src/soc/intel/tigerlake/include/soc/tcss.h @@ -13,24 +13,4 @@ #define IOM_AUX_BIAS_CTRL_PULLDOWN_OFFSET_0 0x1088 #define IOM_AUX_BIAS_CTRL_PULLDOWN_OFFSET(x) (IOM_AUX_BIAS_CTRL_PULLDOWN_OFFSET_0 + (x) * 4) -/* - * The PCI-SIG engineering change requirement provides the ACPI additions for firmware latency - * optimization. Both of FW_RESET_TIME and FW_D3HOT_TO_D0_TIME are applicable to the upstream - * port of the USB4/TBT topology. - */ -/* Number of microseconds to wait after a conventional reset */ -#define FW_RESET_TIME 50000 - -/* Number of microseconds to wait after data link layer active report */ -#define FW_DL_UP_TIME 1 - -/* Number of microseconds to wait after a function level reset */ -#define FW_FLR_RESET_TIME 1 - -/* Number of microseconds to wait from D3 hot to D0 transition */ -#define FW_D3HOT_TO_D0_TIME 50000 - -/* Number of microseconds to wait after setting the VF enable bit */ -#define FW_VF_ENABLE_TIME 1 - #endif /* _SOC_TCSS_H_ */ |