diff options
| -rw-r--r-- | src/soc/amd/picasso/data_fabric.c | 20 | ||||
| -rw-r--r-- | src/soc/amd/picasso/include/soc/data_fabric.h | 16 |
2 files changed, 36 insertions, 0 deletions
diff --git a/src/soc/amd/picasso/data_fabric.c b/src/soc/amd/picasso/data_fabric.c index 79fdba1267..f576d89857 100644 --- a/src/soc/amd/picasso/data_fabric.c +++ b/src/soc/amd/picasso/data_fabric.c @@ -167,3 +167,23 @@ static const struct pci_driver data_fabric_driver __pci_driver = { .vendor = PCI_VENDOR_ID_AMD, .devices = pci_device_ids, }; + +uint32_t data_fabric_read_reg32(uint8_t function, uint16_t reg, uint8_t instance_id) +{ + uint32_t fabric_indirect_access_reg = 0; + + if (instance_id == BROADCAST_FABRIC_ID) + /* No bit masking required. Macros will apply mask to values. */ + return pci_read_config32(_SOC_DEV(DF_DEV, function), reg); + + fabric_indirect_access_reg |= DF_IND_CFG_INST_ACC_EN; + /* Register offset field [10:2] in this register corresponds to [10:2] of the + requested offset. */ + fabric_indirect_access_reg |= reg & DF_IND_CFG_ACC_REG_MASK; + fabric_indirect_access_reg |= + (function << DF_IND_CFG_ACC_FUN_SHIFT) & DF_IND_CFG_ACC_FUN_MASK; + fabric_indirect_access_reg |= instance_id << DF_IND_CFG_INST_ID_SHIFT; + pci_write_config32(SOC_DF_F4_DEV, DF_FICAA_BIOS, fabric_indirect_access_reg); + + return pci_read_config32(SOC_DF_F4_DEV, DF_FICAD_LO); +} diff --git a/src/soc/amd/picasso/include/soc/data_fabric.h b/src/soc/amd/picasso/include/soc/data_fabric.h index 842cb946a7..01fdc73388 100644 --- a/src/soc/amd/picasso/include/soc/data_fabric.h +++ b/src/soc/amd/picasso/include/soc/data_fabric.h @@ -7,6 +7,7 @@ /* D18F0 - Fabric Configuration registers */ #define IOMS0_FABRIC_ID 9 +#define BROADCAST_FABRIC_ID 0xff #define D18F0_VGAEN 0x80 #define VGA_ADDR_ENABLE BIT(0) @@ -24,6 +25,21 @@ #define NB_MMIO_LIMIT(reg) ((reg) * 4 * sizeof(uint32_t) + D18F0_MMIO_LIMIT0) #define NB_MMIO_CONTROL(reg) ((reg) * 4 * sizeof(uint32_t) + D18F0_MMIO_CTRL0) +#define DF_FICAA_BIOS 0x5C +#define DF_FICAD_LO 0x98 +#define DF_FICAD_HI 0x9C + +#define DF_IND_CFG_INST_ACC_EN (1 << 0) +#define DF_IND_CFG_ACC_REG_SHIFT 2 +#define DF_IND_CFG_ACC_REG_MASK (0x1ff << DF_IND_CFG_ACC_REG_SHIFT) +#define DF_IND_CFG_ACC_FUN_SHIFT 11 +#define DF_IND_CFG_ACC_FUN_MASK (0x7 << DF_IND_CFG_ACC_REG_SHIFT) +#define DF_IND_CFG_64B_EN_SHIFT 14 +#define DF_IND_CFG_64B_EN (0x1 << DF_IND_CFG_ACC_REG_SHIFT) +#define DF_IND_CFG_INST_ID_SHIFT 16 +#define DF_IND_CFG_INST_ID_MASK (0xff << DF_IND_CFG_ACC_REG_SHIFT) + void data_fabric_set_mmio_np(void); +uint32_t data_fabric_read_reg32(uint8_t function, uint16_t reg, uint8_t instance_id); #endif /* AMD_PICASSO_DATA_FABRIC_H */ |