diff options
| -rw-r--r-- | src/mainboard/intel/amenia/acpi/ec.asl | 26 | ||||
| -rw-r--r-- | src/mainboard/intel/amenia/acpi/mainboard.asl | 26 | ||||
| -rw-r--r-- | src/mainboard/intel/amenia/dsdt.asl | 7 | ||||
| -rw-r--r-- | src/mainboard/intel/amenia/ec.h | 4 |
4 files changed, 62 insertions, 1 deletions
diff --git a/src/mainboard/intel/amenia/acpi/ec.asl b/src/mainboard/intel/amenia/acpi/ec.asl new file mode 100644 index 0000000000..fe53cb5559 --- /dev/null +++ b/src/mainboard/intel/amenia/acpi/ec.asl @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* mainboard configuration */ +#include "../ec.h" + +/* Enable EC backed ALS device in ACPI */ +#define EC_ENABLE_ALS_DEVICE + +/* Enable EC backed PD MCU device in ACPI */ +#define EC_ENABLE_PD_MCU_DEVICE + +/* ACPI code for EC functions */ +#include <ec/google/chromeec/acpi/ec.asl> diff --git a/src/mainboard/intel/amenia/acpi/mainboard.asl b/src/mainboard/intel/amenia/acpi/mainboard.asl index 09ef9b4e34..c83f48f837 100644 --- a/src/mainboard/intel/amenia/acpi/mainboard.asl +++ b/src/mainboard/intel/amenia/acpi/mainboard.asl @@ -16,6 +16,23 @@ */ #include <soc/gpio_defs.h> +Scope (\_SB) +{ + Device (LID0) + { + Name (_HID, EisaId ("PNP0C0D")) + Method (_LID, 0) + { + Return (\_SB.PCI0.LPCB.EC0.LIDS) + } + } + + Device (PWRB) + { + Name (_HID, EisaId ("PNP0C0C")) + } +} + Scope (\_SB.PCI0.I2C4) { /* Standard Mode: HCNT, LCNT, SDA Hold Register */ @@ -91,3 +108,12 @@ Scope (\_SB.PCI0.I2C3) } } } + +/* + * LPC Trusted Platform Module + */ +Scope (\_SB.PCI0.LPCB) +{ + #include <drivers/pc80/tpm/acpi/tpm.asl> + #include "ec.asl" +} diff --git a/src/mainboard/intel/amenia/dsdt.asl b/src/mainboard/intel/amenia/dsdt.asl index 19e73605dd..4a64f87382 100644 --- a/src/mainboard/intel/amenia/dsdt.asl +++ b/src/mainboard/intel/amenia/dsdt.asl @@ -24,6 +24,12 @@ DefinitionBlock( 0x20110725 // OEM revision ) { + /* global NVS and variables */ + #include <soc/intel/apollolake/acpi/globalnvs.asl> + + /* CPU */ + #include <soc/intel/apollolake/acpi/cpu.asl> + Scope (\_SB) { Device (PCI0) { @@ -38,5 +44,4 @@ DefinitionBlock( #include <soc/intel/apollolake/acpi/sleepstates.asl> #include "acpi/superio.asl" - } diff --git a/src/mainboard/intel/amenia/ec.h b/src/mainboard/intel/amenia/ec.h index ab8bcbada8..91890fd63e 100644 --- a/src/mainboard/intel/amenia/ec.h +++ b/src/mainboard/intel/amenia/ec.h @@ -20,6 +20,10 @@ #include <ec/google/chromeec/ec_commands.h> +/* This is the GPE status bit. + TODO: Fix this to proper bit matching GPE routing table */ +#define EC_SCI_GPI 15 + #define MAINBOARD_EC_SCI_EVENTS \ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ |