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-rw-r--r--src/cpu/intel/common/common_init.c204
-rw-r--r--src/include/acpi/acpi.h4
-rw-r--r--src/soc/amd/cezanne/cppc.c177
3 files changed, 63 insertions, 322 deletions
diff --git a/src/cpu/intel/common/common_init.c b/src/cpu/intel/common/common_init.c
index c5f43ef22e..6203922fd8 100644
--- a/src/cpu/intel/common/common_init.c
+++ b/src/cpu/intel/common/common_init.c
@@ -103,184 +103,44 @@ void set_feature_ctrl_lock(void)
*/
void cpu_init_cppc_config(struct cppc_config *config, u32 version)
{
- acpi_addr_t msr = {
- .space_id = ACPI_ADDRESS_SPACE_FIXED,
- .bit_width = 8,
- .bit_offset = 0,
- .access_size = ACPI_ACCESS_SIZE_QWORD_ACCESS,
- .addrl = 0,
- .addrh = 0,
- };
- static const acpi_addr_t unsupported = {
- .space_id = ACPI_ADDRESS_SPACE_MEMORY,
- .bit_width = 0,
- .bit_offset = 0,
- .access_size = ACPI_ACCESS_SIZE_UNDEFINED,
- .addrl = 0,
- .addrh = 0,
- };
-
config->version = version;
- msr.addrl = IA32_HWP_CAPABILITIES;
-
- /*
- * Highest Performance:
- * ResourceTemplate(){Register(FFixedHW, 0x08, 0x00, 0x771, 0x04,)},
- */
- config->regs[CPPC_HIGHEST_PERF] = msr;
-
- /*
- * Lowest Nonlinear Performance -> Most Efficient Performance:
- * ResourceTemplate(){Register(FFixedHW, 0x08, 0x10, 0x771, 0x04,)},
- */
- msr.bit_offset = 16;
- config->regs[CPPC_LOWEST_NONL_PERF] = msr;
-
- /*
- * Lowest Performance:
- * ResourceTemplate(){Register(FFixedHW, 0x08, 0x18, 0x771, 0x04,)},
- */
- msr.bit_offset = 24;
- config->regs[CPPC_LOWEST_PERF] = msr;
-
- /*
- * Guaranteed Performance Register:
- * ResourceTemplate(){Register(FFixedHW, 0x08, 0x08, 0x771, 0x04,)},
- */
- msr.bit_offset = 8;
- config->regs[CPPC_GUARANTEED_PERF] = msr;
-
- msr.addrl = MSR_PLATFORM_INFO;
-
- /*
- * Nominal Performance -> Maximum Non-Turbo Ratio:
- * ResourceTemplate(){Register(FFixedHW, 0x08, 0x08, 0xce, 0x04,)},
- */
- msr.bit_offset = 8;
- config->regs[CPPC_NOMINAL_PERF] = msr;
-
- msr.addrl = IA32_HWP_REQUEST;
-
- /*
- * Desired Performance Register:
- * ResourceTemplate(){Register(FFixedHW, 0x08, 0x10, 0x774, 0x04,)},
- */
- msr.bit_offset = 16;
- config->regs[CPPC_DESIRED_PERF] = msr;
-
- /*
- * Minimum Performance Register:
- * ResourceTemplate(){Register(FFixedHW, 0x08, 0x00, 0x774, 0x04,)},
- */
- msr.bit_offset = 0;
- config->regs[CPPC_MIN_PERF] = msr;
-
- /*
- * Maximum Performance Register:
- * ResourceTemplate(){Register(FFixedHW, 0x08, 0x08, 0x774, 0x04,)},
- */
- msr.bit_offset = 8;
- config->regs[CPPC_MAX_PERF] = msr;
-
- /*
- * Performance Reduction Tolerance Register:
- * ResourceTemplate(){Register(SystemMemory, 0x00, 0x00, 0x0,,)},
- */
- config->regs[CPPC_PERF_REDUCE_TOLERANCE] = unsupported;
-
- /*
- * Time Window Register:
- * ResourceTemplate(){Register(SystemMemory, 0x00, 0x00, 0x0,,)},
- */
- config->regs[CPPC_TIME_WINDOW] = unsupported;
-
- /*
- * Counter Wraparound Time:
- * ResourceTemplate(){Register(SystemMemory, 0x00, 0x00, 0x0,,)},
- */
- config->regs[CPPC_COUNTER_WRAP] = unsupported;
-
- msr.addrl = IA32_MPERF;
-
- /*
- * Reference Performance Counter Register:
- * ResourceTemplate(){Register(FFixedHW, 0x40, 0x00, 0x0E7, 0x04,)},
- */
- msr.bit_width = 64;
- msr.bit_offset = 0;
- config->regs[CPPC_REF_PERF_COUNTER] = msr;
-
- msr.addrl = IA32_APERF;
-
- /*
- * Delivered Performance Counter Register:
- * ResourceTemplate(){Register(FFixedHW, 0x40, 0x00, 0x0E8, 0x04,)},
- */
- config->regs[CPPC_DELIVERED_PERF_COUNTER] = msr;
-
- msr.addrl = IA32_HWP_STATUS;
-
- /*
- * Performance Limited Register:
- * ResourceTemplate(){Register(FFixedHW, 0x01, 0x02, 0x777, 0x04,)},
- */
- msr.bit_width = 1;
- msr.bit_offset = 2;
- config->regs[CPPC_PERF_LIMITED] = msr;
-
- msr.addrl = IA32_PM_ENABLE;
-
- /*
- * CPPC Enable Register:
- * ResourceTemplate(){Register(FFixedHW, 0x01, 0x00, 0x770, 0x04,)},
- */
- msr.bit_offset = 0;
- config->regs[CPPC_ENABLE] = msr;
-
- if (version >= 2) {
- /* Autonomous Selection Enable is populated below */
+ config->regs[CPPC_HIGHEST_PERF] = ACPI_REG_MSR(IA32_HWP_CAPABILITIES, 0, 8);
+ config->regs[CPPC_NOMINAL_PERF] = ACPI_REG_MSR(MSR_PLATFORM_INFO, 8, 8);
+ config->regs[CPPC_LOWEST_NONL_PERF] = ACPI_REG_MSR(IA32_HWP_CAPABILITIES, 16, 8);
+ config->regs[CPPC_LOWEST_PERF] = ACPI_REG_MSR(IA32_HWP_CAPABILITIES, 24, 8);
+ config->regs[CPPC_GUARANTEED_PERF] = ACPI_REG_MSR(IA32_HWP_CAPABILITIES, 8, 8);
+ config->regs[CPPC_DESIRED_PERF] = ACPI_REG_MSR(IA32_HWP_REQUEST, 16, 8);
+ config->regs[CPPC_MIN_PERF] = ACPI_REG_MSR(IA32_HWP_REQUEST, 0, 8);
+ config->regs[CPPC_MAX_PERF] = ACPI_REG_MSR(IA32_HWP_REQUEST, 8, 8);
+ config->regs[CPPC_PERF_REDUCE_TOLERANCE] = ACPI_REG_UNSUPPORTED;
+ config->regs[CPPC_TIME_WINDOW] = ACPI_REG_UNSUPPORTED;
+ config->regs[CPPC_COUNTER_WRAP] = ACPI_REG_UNSUPPORTED;
+ config->regs[CPPC_REF_PERF_COUNTER] = ACPI_REG_MSR(IA32_MPERF, 0, 64);
+ config->regs[CPPC_DELIVERED_PERF_COUNTER] = ACPI_REG_MSR(IA32_APERF, 0, 64);
+ config->regs[CPPC_PERF_LIMITED] = ACPI_REG_MSR(IA32_HWP_STATUS, 2, 1);
+ config->regs[CPPC_ENABLE] = ACPI_REG_MSR(IA32_PM_ENABLE, 0, 1);
+
+ if (version < 2)
+ return;
- msr.addrl = IA32_HWP_REQUEST;
+ config->regs[CPPC_AUTO_SELECT] = (acpi_addr_t){
+ .space_id = ACPI_ADDRESS_SPACE_MEMORY,
+ .bit_width = 32,
+ .bit_offset = 0,
+ .access_size = ACPI_ACCESS_SIZE_UNDEFINED,
+ .addrl = 1,
+ };
- /*
- * Autonomous Activity Window Register
- * ResourceTemplate(){Register(FFixedHW, 0x0a, 0x20, 0x774, 0x04,)},
- */
- msr.bit_width = 10;
- msr.bit_offset = 32;
- config->regs[CPPC_AUTO_ACTIVITY_WINDOW] = msr;
+ config->regs[CPPC_AUTO_ACTIVITY_WINDOW] = ACPI_REG_MSR(IA32_HWP_REQUEST, 32, 10);
+ config->regs[CPPC_PERF_PREF] = ACPI_REG_MSR(IA32_HWP_REQUEST, 24, 8);
+ config->regs[CPPC_REF_PERF] = ACPI_REG_UNSUPPORTED;
- /*
- * Autonomous Energy Performance Preference Register
- * ResourceTemplate(){Register(FFixedHW, 0x08, 0x18, 0x774, 0x04,)},
- */
- msr.bit_width = 8;
- msr.bit_offset = 24;
- config->regs[CPPC_PERF_PREF] = msr;
-
- /* Reference Performance */
- config->regs[CPPC_REF_PERF] = unsupported;
-
- if (version >= 3) {
- /* Lowest Frequency */
- config->regs[CPPC_LOWEST_FREQ] = unsupported;
- /* Nominal Frequency */
- config->regs[CPPC_NOMINAL_FREQ] = unsupported;
- }
+ if (version < 3)
+ return;
- /*
- * Autonomous Selection Enable = 1
- * This field is actually the first addition in version 2 but
- * it's so unlike the others I'm populating it last.
- */
- msr.space_id = ACPI_ADDRESS_SPACE_MEMORY;
- msr.bit_width = 32;
- msr.bit_offset = 0;
- msr.access_size = ACPI_ACCESS_SIZE_UNDEFINED;
- msr.addrl = 1;
- config->regs[CPPC_AUTO_SELECT] = msr;
- }
+ config->regs[CPPC_LOWEST_FREQ] = ACPI_REG_UNSUPPORTED;
+ config->regs[CPPC_NOMINAL_FREQ] = ACPI_REG_UNSUPPORTED;
}
void set_aesni_lock(void)
diff --git a/src/include/acpi/acpi.h b/src/include/acpi/acpi.h
index e35accdf78..bc0b30c720 100644
--- a/src/include/acpi/acpi.h
+++ b/src/include/acpi/acpi.h
@@ -130,7 +130,7 @@ typedef struct acpi_gen_regaddr {
/* Macros for common resource types */
#define ACPI_REG_MSR(address, offset, width) \
- { \
+ (acpi_addr_t){ \
.space_id = ACPI_ADDRESS_SPACE_FIXED, \
.access_size = ACPI_ACCESS_SIZE_QWORD_ACCESS, \
.addrl = address, \
@@ -138,7 +138,7 @@ typedef struct acpi_gen_regaddr {
.bit_width = width, \
}
-#define ACPI_REG_UNSUPPORTED {0}
+#define ACPI_REG_UNSUPPORTED (acpi_addr_t){0}
/* Common ACPI HIDs */
#define ACPI_HID_FDC "PNP0700"
diff --git a/src/soc/amd/cezanne/cppc.c b/src/soc/amd/cezanne/cppc.c
index 79292a4153..9d681c6ba7 100644
--- a/src/soc/amd/cezanne/cppc.c
+++ b/src/soc/amd/cezanne/cppc.c
@@ -13,156 +13,37 @@
*/
void cpu_init_cppc_config(struct cppc_config *config, u32 version)
{
- acpi_addr_t msr = {
- .space_id = ACPI_ADDRESS_SPACE_FIXED,
- .bit_width = 8,
- .bit_offset = 0,
- .access_size = ACPI_ACCESS_SIZE_QWORD_ACCESS,
- .addrl = 0,
- .addrh = 0,
- };
- static const acpi_addr_t unsupported = {
- .space_id = ACPI_ADDRESS_SPACE_MEMORY,
- .bit_width = 0,
- .bit_offset = 0,
- .access_size = ACPI_ACCESS_SIZE_UNDEFINED,
- .addrl = 0,
- .addrh = 0,
- };
-
config->version = version;
- /*
- * Highest Performance:
- */
- msr.addrl = MSR_CPPC_CAPABILITY_1;
- msr.bit_offset = SHIFT_CPPC_CAPABILITY_1_HIGHEST_PERF;
- config->regs[CPPC_HIGHEST_PERF] = msr;
-
- /*
- * Lowest Nonlinear Performance -> Most Efficient Performance:
- */
- msr.bit_offset = SHIFT_CPPC_CAPABILITY_1_LOW_NON_LIN_PERF;
- config->regs[CPPC_LOWEST_NONL_PERF] = msr;
-
- /*
- * Lowest Performance:
- */
- msr.bit_offset = SHIFT_CPPC_CAPABILITY_1_LOWEST_PERF;
- config->regs[CPPC_LOWEST_PERF] = msr;
-
- /*
- * Guaranteed Performance Register:
- */
- config->regs[CPPC_GUARANTEED_PERF] = unsupported;
-
- /*
- * Nominal Performance -> Maximum Non-Turbo Ratio:
- */
- msr.bit_offset = SHIFT_CPPC_CAPABILITY_1_NOMINAL_PERF;
- config->regs[CPPC_NOMINAL_PERF] = msr;
-
- /*
- * Desired Performance Register:
- */
- msr.addrl = MSR_CPPC_REQUEST;
- msr.bit_offset = SHIFT_CPPC_REQUEST_DES_PERF;
- config->regs[CPPC_DESIRED_PERF] = msr;
-
- /*
- * Minimum Performance Register:
- */
- msr.bit_offset = SHIFT_CPPC_REQUEST_MIN_PERF;
- config->regs[CPPC_MIN_PERF] = msr;
-
- /*
- * Maximum Performance Register:
- */
- msr.bit_offset = SHIFT_CPPC_REQUEST_MAX_PERF;
- config->regs[CPPC_MAX_PERF] = msr;
-
- /*
- * Performance Reduction Tolerance Register:
- */
- config->regs[CPPC_PERF_REDUCE_TOLERANCE] = unsupported;
-
- /*
- * Time Window Register:
- */
- config->regs[CPPC_TIME_WINDOW] = unsupported;
-
- /*
- * Counter Wraparound Time:
- */
- config->regs[CPPC_COUNTER_WRAP] = unsupported;
-
- /*
- * Reference Performance Counter Register:
- */
- msr.addrl = MSR_MAX_PERFORMANCE_FREQUENCY_CLOCK_COUNT;
- msr.bit_width = 64;
- msr.bit_offset = 0;
- config->regs[CPPC_REF_PERF_COUNTER] = msr;
-
- /*
- * Delivered Performance Counter Register:
- */
- msr.addrl = MSR_ACTUAL_PERFORMANCE_FREQUENCY_CLOCK_COUNT;
- config->regs[CPPC_DELIVERED_PERF_COUNTER] = msr;
-
- /*
- * Performance Limited Register:
- */
- msr.bit_width = 1;
- msr.addrl = MSR_CPPC_STATUS;
- msr.bit_offset = 1;
- config->regs[CPPC_PERF_LIMITED] = msr;
-
- /*
- * CPPC Enable Register:
- */
- msr.addrl = MSR_CPPC_ENABLE;
- msr.bit_offset = 0;
- config->regs[CPPC_ENABLE] = msr;
-
- if (version >= 2) {
- /* Autonomous Selection Enable is populated below */
-
- /*
- * Autonomous Activity Window Register
- */
- config->regs[CPPC_AUTO_ACTIVITY_WINDOW] = unsupported;
-
- /*
- * Autonomous Energy Performance Preference Register
- */
- msr.addrl = MSR_CPPC_REQUEST;
- msr.bit_width = 8;
- msr.bit_offset = SHIFT_CPPC_REQUEST_ENERGY_PERF_PREF;
- config->regs[CPPC_PERF_PREF] = msr;
-
- /* Reference Performance */
- config->regs[CPPC_REF_PERF] = unsupported;
-
- if (version >= 3) {
- /* Lowest Frequency */
- config->regs[CPPC_LOWEST_FREQ] = unsupported;
- /* Nominal Frequency */
- config->regs[CPPC_NOMINAL_FREQ] = unsupported;
- }
-
- /*
- * Autonomous Selection Enable = 1
- * This field is actually the first addition in version 2 but
- * it's so unlike the others I'm populating it last.
- */
- msr.space_id = ACPI_ADDRESS_SPACE_MEMORY;
- msr.bit_width = 32;
- msr.bit_offset = 0;
- msr.access_size = ACPI_ACCESS_SIZE_UNDEFINED;
- msr.addrl = 1;
- config->regs[CPPC_AUTO_SELECT] = unsupported;
- }
+ config->regs[CPPC_HIGHEST_PERF] = ACPI_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_HIGHEST_PERF, 8);
+ config->regs[CPPC_NOMINAL_PERF] = ACPI_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_NOMINAL_PERF, 8);
+ config->regs[CPPC_LOWEST_NONL_PERF] = ACPI_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_LOW_NON_LIN_PERF, 8);
+ config->regs[CPPC_LOWEST_PERF] = ACPI_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_LOWEST_PERF, 8);
+ config->regs[CPPC_GUARANTEED_PERF] = ACPI_REG_UNSUPPORTED;
+ config->regs[CPPC_DESIRED_PERF] = ACPI_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_DES_PERF, 8);
+ config->regs[CPPC_MIN_PERF] = ACPI_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_MIN_PERF, 8);
+ config->regs[CPPC_MAX_PERF] = ACPI_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_MAX_PERF, 8);
+ config->regs[CPPC_PERF_REDUCE_TOLERANCE] = ACPI_REG_UNSUPPORTED;
+ config->regs[CPPC_TIME_WINDOW] = ACPI_REG_UNSUPPORTED;
+ config->regs[CPPC_COUNTER_WRAP] = ACPI_REG_UNSUPPORTED;
+ config->regs[CPPC_REF_PERF_COUNTER] = ACPI_REG_MSR(MSR_MAX_PERFORMANCE_FREQUENCY_CLOCK_COUNT, 0, 64);
+ config->regs[CPPC_DELIVERED_PERF_COUNTER] = ACPI_REG_MSR(MSR_ACTUAL_PERFORMANCE_FREQUENCY_CLOCK_COUNT, 0, 64);
+ config->regs[CPPC_PERF_LIMITED] = ACPI_REG_MSR(MSR_CPPC_STATUS, 1, 1);
+ config->regs[CPPC_ENABLE] = ACPI_REG_MSR(MSR_CPPC_ENABLE, 0, 1);
+
+ if (version < 2)
+ return;
+
+ config->regs[CPPC_AUTO_SELECT] = ACPI_REG_UNSUPPORTED;
+ config->regs[CPPC_AUTO_ACTIVITY_WINDOW] = ACPI_REG_UNSUPPORTED;
+ config->regs[CPPC_PERF_PREF] = ACPI_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_ENERGY_PERF_PREF, 8);
+ config->regs[CPPC_REF_PERF] = ACPI_REG_UNSUPPORTED;
+
+ if (version < 3)
+ return;
+
+ config->regs[CPPC_LOWEST_FREQ] = ACPI_REG_UNSUPPORTED;
+ config->regs[CPPC_NOMINAL_FREQ] = ACPI_REG_UNSUPPORTED;
}
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-10 09:24:46 +0000