diff options
8 files changed, 10 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/brask/overridetree.cb b/src/mainboard/google/brya/variants/brask/overridetree.cb index d60183bcb7..b9c8edbe4f 100644 --- a/src/mainboard/google/brya/variants/brask/overridetree.cb +++ b/src/mainboard/google/brya/variants/brask/overridetree.cb @@ -97,6 +97,7 @@ chip soc/intel/alderlake register "cpu_pcie_rp[CPU_RP(1)]" = "{ .clk_req = 0, .clk_src = 0, + .flags = PCIE_RP_LTR | PCIE_RP_AER, }" end device ref tcss_dma0 on diff --git a/src/mainboard/google/brya/variants/kano/overridetree.cb b/src/mainboard/google/brya/variants/kano/overridetree.cb index 87148c5d12..684a4aec51 100644 --- a/src/mainboard/google/brya/variants/kano/overridetree.cb +++ b/src/mainboard/google/brya/variants/kano/overridetree.cb @@ -182,6 +182,7 @@ chip soc/intel/alderlake register "cpu_pcie_rp[CPU_RP(1)]" = "{ .clk_req = 0, .clk_src = 0, + .flags = PCIE_RP_LTR | PCIE_RP_AER, }" end device ref tcss_dma0 on diff --git a/src/mainboard/google/brya/variants/taeko/overridetree.cb b/src/mainboard/google/brya/variants/taeko/overridetree.cb index c1c567e7fa..c99777d907 100644 --- a/src/mainboard/google/brya/variants/taeko/overridetree.cb +++ b/src/mainboard/google/brya/variants/taeko/overridetree.cb @@ -228,6 +228,7 @@ chip soc/intel/alderlake register "cpu_pcie_rp[CPU_RP(1)]" = "{ .clk_req = 0, .clk_src = 0, + .flags = PCIE_RP_LTR | PCIE_RP_AER, }" probe BOOT_NVME_MASK BOOT_NVME_ENABLED end diff --git a/src/mainboard/google/brya/variants/taeko4es/overridetree.cb b/src/mainboard/google/brya/variants/taeko4es/overridetree.cb index 5b7b49708e..7609ba6d4d 100644 --- a/src/mainboard/google/brya/variants/taeko4es/overridetree.cb +++ b/src/mainboard/google/brya/variants/taeko4es/overridetree.cb @@ -224,6 +224,7 @@ chip soc/intel/alderlake register "cpu_pcie_rp[CPU_RP(1)]" = "{ .clk_req = 0, .clk_src = 0, + .flags = PCIE_RP_LTR | PCIE_RP_AER, }" end device ref tbt_pcie_rp0 off end diff --git a/src/mainboard/google/brya/variants/taniks/overridetree.cb b/src/mainboard/google/brya/variants/taniks/overridetree.cb index 4b97a48b44..ab98312628 100644 --- a/src/mainboard/google/brya/variants/taniks/overridetree.cb +++ b/src/mainboard/google/brya/variants/taniks/overridetree.cb @@ -221,6 +221,7 @@ chip soc/intel/alderlake register "cpu_pcie_rp[CPU_RP(1)]" = "{ .clk_req = 0, .clk_src = 0, + .flags = PCIE_RP_LTR | PCIE_RP_AER, }" end device ref tbt_pcie_rp0 off end diff --git a/src/mainboard/google/brya/variants/vell/overridetree.cb b/src/mainboard/google/brya/variants/vell/overridetree.cb index 034d496bb9..ed2ccd7765 100644 --- a/src/mainboard/google/brya/variants/vell/overridetree.cb +++ b/src/mainboard/google/brya/variants/vell/overridetree.cb @@ -144,6 +144,7 @@ chip soc/intel/alderlake register "cpu_pcie_rp[CPU_RP(1)]" = "{ .clk_req = 1, .clk_src = 1, + .flags = PCIE_RP_LTR | PCIE_RP_AER, }" end device ref cnvi_wifi on diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb index 2c45e85e34..8f60e42970 100644 --- a/src/mainboard/intel/adlrvp/devicetree.cb +++ b/src/mainboard/intel/adlrvp/devicetree.cb @@ -81,18 +81,21 @@ chip soc/intel/alderlake register "cpu_pcie_rp[CPU_RP(1)]" = "{ .clk_req = 0, .clk_src = 0, + .flags = PCIE_RP_LTR | PCIE_RP_AER, }" # Enable CPU PCIE RP 2 using CLK 3 register "cpu_pcie_rp[CPU_RP(2)]" = "{ .clk_req = 3, .clk_src = 3, + .flags = PCIE_RP_LTR | PCIE_RP_AER, }" # Enable CPU PCIE RP 3 using CLK 4 register "cpu_pcie_rp[CPU_RP(3)]" = "{ .clk_req = 4, .clk_src = 4, + .flags = PCIE_RP_LTR | PCIE_RP_AER, }" register "SataSalpSupport" = "1" diff --git a/src/mainboard/intel/adlrvp/devicetree_m.cb b/src/mainboard/intel/adlrvp/devicetree_m.cb index b73ded1e10..ab9983095b 100644 --- a/src/mainboard/intel/adlrvp/devicetree_m.cb +++ b/src/mainboard/intel/adlrvp/devicetree_m.cb @@ -89,6 +89,7 @@ chip soc/intel/alderlake register "cpu_pcie_rp[CPU_RP(1)]" = "{ .clk_req = 0, .clk_src = 0, + .flags = PCIE_RP_LTR | PCIE_RP_AER, }" # Enable EDP in PortA |