diff options
| -rw-r--r-- | src/soc/intel/meteorlake/Kconfig | 4 | ||||
| -rw-r--r-- | src/soc/intel/meteorlake/fsp_params.c | 13 | ||||
| -rw-r--r-- | src/soc/intel/meteorlake/romstage/fsp_params.c | 20 |
3 files changed, 36 insertions, 1 deletions
diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig index 78c3d5a865..013f123c92 100644 --- a/src/soc/intel/meteorlake/Kconfig +++ b/src/soc/intel/meteorlake/Kconfig @@ -15,13 +15,17 @@ config CPU_SPECIFIC_OPTIONS select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select CPU_SUPPORTS_INTEL_TME select CPU_SUPPORTS_PM_TIMER_EMULATION + select DISPLAY_FSP_VERSION_INFO select DRIVERS_INTEL_USB4_RETIMER select DRIVERS_USB_ACPI select FSP_COMPRESS_FSP_S_LZ4 select FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW select FSP_M_XIP select FSP_STATUS_GLOBAL_RESET_REQUIRED_3 + select FSP_USES_CB_DEBUG_EVENT_HANDLER + select FSPS_HAS_ARCH_UPD select GENERIC_GPIO_LIB + select HAVE_DEBUG_RAM_SETUP select HAVE_FSP_GOP select INTEL_DESCRIPTOR_MODE_CAPABLE select HAVE_SMI_HANDLER diff --git a/src/soc/intel/meteorlake/fsp_params.c b/src/soc/intel/meteorlake/fsp_params.c index ad02ac58ab..e030948ff8 100644 --- a/src/soc/intel/meteorlake/fsp_params.c +++ b/src/soc/intel/meteorlake/fsp_params.c @@ -7,6 +7,7 @@ #include <device/device.h> #include <device/pci.h> #include <fsp/api.h> +#include <fsp/fsp_debug_event.h> #include <fsp/ppi/mp_service_ppi.h> #include <fsp/util.h> #include <intelblocks/cse.h> @@ -241,6 +242,17 @@ static void fill_fsps_xdci_params(FSP_S_CONFIG *s_cfg, s_cfg->XdciEnable = xdci_can_enable(PCI_DEVFN_USBOTG); } +static void fill_fsps_uart_params(FSP_S_CONFIG *s_cfg, + const struct soc_intel_meteorlake_config *config) +{ + if (CONFIG(FSP_USES_CB_DEBUG_EVENT_HANDLER) && CONFIG(CONSOLE_SERIAL) && + CONFIG(FSP_ENABLE_SERIAL_DEBUG)) + s_cfg->FspEventHandler = (UINT32)((FSP_EVENT_HANDLER *) + fsp_debug_event_handler); + ASSERT(ARRAY_SIZE(s_cfg->SerialIoUartAutoFlow) > CONFIG_UART_FOR_CONSOLE); + s_cfg->SerialIoUartAutoFlow[CONFIG_UART_FOR_CONSOLE] = 0; +} + static void fill_fsps_sata_params(FSP_S_CONFIG *s_cfg, const struct soc_intel_meteorlake_config *config) { @@ -423,6 +435,7 @@ static void soc_silicon_init_params(FSP_S_CONFIG *s_cfg, fill_fsps_chipset_lockdown_params, fill_fsps_xhci_params, fill_fsps_xdci_params, + fill_fsps_uart_params, fill_fsps_sata_params, fill_fsps_thermal_params, fill_fsps_lan_params, diff --git a/src/soc/intel/meteorlake/romstage/fsp_params.c b/src/soc/intel/meteorlake/romstage/fsp_params.c index 45d9415dfc..c9fdf79f34 100644 --- a/src/soc/intel/meteorlake/romstage/fsp_params.c +++ b/src/soc/intel/meteorlake/romstage/fsp_params.c @@ -4,6 +4,7 @@ #include <console/console.h> #include <cpu/x86/msr.h> #include <device/device.h> +#include <fsp/fsp_debug_event.h> #include <fsp/util.h> #include <intelblocks/cpulib.h> #include <intelblocks/pcie_rp.h> @@ -284,7 +285,24 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) { const struct soc_intel_meteorlake_config *config; FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; - + FSPM_ARCH_UPD *arch_upd = &mupd->FspmArchUpd; + + if (CONFIG(FSP_USES_CB_DEBUG_EVENT_HANDLER)) { + if (CONFIG(CONSOLE_SERIAL) && CONFIG(FSP_ENABLE_SERIAL_DEBUG)) { + enum fsp_log_level log_level = fsp_map_console_log_level(); + arch_upd->FspEventHandler = (UINT32)((FSP_EVENT_HANDLER *) + fsp_debug_event_handler); + /* Set Serial debug message level */ + m_cfg->PcdSerialDebugLevel = log_level; + /* Set MRC debug level */ + m_cfg->SerialDebugMrcLevel = log_level; + } else { + /* Disable Serial debug message */ + m_cfg->PcdSerialDebugLevel = 0; + /* Disable MRC debug message */ + m_cfg->SerialDebugMrcLevel = 0; + } + } config = config_of_soc(); soc_memory_init_params(m_cfg, config); |