diff options
22 files changed, 4 insertions, 756 deletions
diff --git a/src/northbridge/via/cx700/early_smbus.c b/src/northbridge/via/cx700/early_smbus.c index 44aa743f88..b501baf3a3 100644 --- a/src/northbridge/via/cx700/early_smbus.c +++ b/src/northbridge/via/cx700/early_smbus.c @@ -102,7 +102,6 @@ static void smbus_reset(void) /* Public functions */ static void set_ics_data(unsigned char dev, int data, char len) { - //int i; smbus_reset(); /* clear host data port */ outb(0x00, SMBHSTDAT0); @@ -114,7 +113,6 @@ static void set_ics_data(unsigned char dev, int data, char len) /* fill blocktransfer array */ if (dev == 0xd2) { - //char d2_data[] = {0x0d,0x00,0x3f,0xcd,0x7f,0xbf,0x1a,0x2a,0x01,0x0f,0x0b,0x00,0x8d,0x9b}; outb(0x0d, SMBBLKDAT); outb(0x00, SMBBLKDAT); outb(0x3f, SMBBLKDAT); @@ -130,7 +128,6 @@ static void set_ics_data(unsigned char dev, int data, char len) outb(0x8d, SMBBLKDAT); outb(0x9b, SMBBLKDAT); } else { - //char d4_data[] = {0x08,0xff,0x3f,0x00,0x00,0xff,0xff,0xff,0xff}; outb(0x08, SMBBLKDAT); outb(0xff, SMBBLKDAT); outb(0x3f, SMBBLKDAT); @@ -142,9 +139,6 @@ static void set_ics_data(unsigned char dev, int data, char len) outb(0xff, SMBBLKDAT); } - //for (i = 0; i < len; i++) - // outb(data[i],SMBBLKDAT); - outb(dev, SMBXMITADD); outb(0, SMBHSTCMD); outb(len, SMBHSTDAT0); diff --git a/src/northbridge/via/cx700/lpc.c b/src/northbridge/via/cx700/lpc.c index e9e4d98e33..c90dab7b84 100644 --- a/src/northbridge/via/cx700/lpc.c +++ b/src/northbridge/via/cx700/lpc.c @@ -110,7 +110,6 @@ static void setup_pm(device_t dev) /* GP2 Timer Counter */ pci_write_config8(dev, 0x99, 0xfb); /* GP3 Timer Counter */ - //pci_write_config8(dev, 0x9a, 0x20); /* Multi Function Select 1 */ pci_write_config8(dev, 0xe4, 0x00); @@ -169,7 +168,6 @@ static void cx700_set_lpc_registers(struct device *dev) pci_write_config8(dev, 0x6C, enables); // Map 4MB of FLASH into the address space -// pci_write_config8(dev, 0x41, 0x7f); // Set bit 6 of 0x40, because Award does it (IO recovery time) // IMPORTANT FIX - EISA 0x4d0 decoding must be on so that PCI diff --git a/src/northbridge/via/cx700/raminit.c b/src/northbridge/via/cx700/raminit.c index aad851d929..f8d709c135 100644 --- a/src/northbridge/via/cx700/raminit.c +++ b/src/northbridge/via/cx700/raminit.c @@ -815,7 +815,6 @@ static void sdram_set_safe_values(const struct mem_controller *ctrl) /* Clock Phase Control for FeedBack Mode */ regs = pci_read_config8(MEMCTRL, 0x90); -// regs |= 0x80; pci_write_config8(MEMCTRL, 0x90, regs); regs = pci_read_config8(PCI_DEV(0, 0, 4), SCRATCH_DRAM_FREQ); @@ -1343,13 +1342,6 @@ static void sdram_enable(const struct mem_controller *ctrl) /****************************************************************/ /* Find out the lowest Bank Interleave and Set Register */ /****************************************************************/ -#if 0 - //TODO - reg8 = pci_read_config8(MEMCTRL, 0x69); - reg8 &= ~0xc0; - reg8 |= 0x80; //8 banks - pci_write_config8(MEMCTRL, 0x69, reg8); -#endif dl = 2; for (i = 0; i < 4; i++) { reg8 = pci_read_config8(PCI_DEV(0, 0, 4), (SCRATCH_RANK_0 + i)); diff --git a/src/northbridge/via/vx800/detection.c b/src/northbridge/via/vx800/detection.c index ce643a0059..bbedd38b6b 100644 --- a/src/northbridge/via/vx800/detection.c +++ b/src/northbridge/via/vx800/detection.c @@ -52,8 +52,6 @@ CB_STATUS DRAMDetect(DRAM_SYS_ATTR *DramAttr) if (CB_SUCCESS == Status) { /* 64bit or 128Bit */ - // if (RAMTYPE_SDRAMDDR == DramAttr->DramType) - /* Select command rate. */ DRAMCmdRate(DramAttr); } diff --git a/src/northbridge/via/vx800/dev_init.c b/src/northbridge/via/vx800/dev_init.c index 7ac5fe1999..1bc779f16a 100644 --- a/src/northbridge/via/vx800/dev_init.c +++ b/src/northbridge/via/vx800/dev_init.c @@ -61,10 +61,7 @@ static const u8 DramRegTbl[][3] = { * R/W DRAM. */ - // {0x79, 0x00, 0x8F }, {0x85, 0x00, 0x00}, - // {0x90, 0x87, 0x78 }, - // {0x91, 0x00, 0x46 }, {0x40, 0x00, 0x00}, {0, 0, 0} @@ -94,9 +91,6 @@ void DRAMRegInitValue(DRAM_SYS_ATTR *DramAttr) Data |= 0x0; /* CHA + CHC */ pci_write_config8(MEMCTRL, 0x6c, Data); - // Data = 0xAA; - // pci_write_config8(MEMCTRL, 0xb1, Data); - // set CHB DQSB input delay, or else will meet error which // is some byte is right but another bit is error. Data = pci_read_config8(MEMCTRL, 0xff); @@ -104,9 +98,6 @@ void DRAMRegInitValue(DRAM_SYS_ATTR *DramAttr) pci_write_config8(MEMCTRL, 0xff, Data); // enable CHC RXDB[7] - // Data = pci_read_config8(MEMCTRL, 0xdb); - // Data = (Data & 0x7F) | 0x80; - // pci_write_config8(MEMCTRL, 0xdb, Data); // rx62[2:0], CHA and CHB CL Data = pci_read_config8(MEMCTRL, 0x62); @@ -473,7 +464,7 @@ void InitDDR2CHA(DRAM_SYS_ATTR *DramAttr) Twr = (Data & 0xE0) >> 5; AccessAddr += CHA_DDR2_Twr_table[Twr]; - // AccessAddr = 0x1012D8; + DimmRead(AccessAddr); /* Set MRS command. */ PRINT_DEBUG_MEM("Step 18 Address"); PRINT_DEBUG_MEM_HEX32(AccessAddr); @@ -517,358 +508,6 @@ void InitDDR2CHA(DRAM_SYS_ATTR *DramAttr) } /*=================================================================== -Function : InitDDR2_CHB() -Precondition : -Input : - DramAttr: pointer point to DRAM_SYS_ATTR which consist the DDR and Dimm information - in MotherBoard -Output : Void -Purpose : Initialize DDR2 of CHB by standard sequence -Reference : -===================================================================*/ -/*// DLL: Enable Reset -static const u32 CHB_MRS_DLL_150[2] = { 0x00020200 | (1 << 20), 0x00000800 }; // with 150 ohm (A17 = 1, A9 = 1), (A11 = 1)(cpu address) -//u32 CHB_MRS_DLL_75[2] = { 0x00020020 | (1 << 20), 0x00000800 }; // with 75 ohm (A17 = 1, A5 = 1), (A11 = 1)(cpu address) -// CPU(DRAM) -// { DLL: Enable. A17(BA0)=1 and A3(MA0)=0 } -// { DLL: reset. A11(MA8)=1 } -// -// DDR2 CL = 2 CL = 3 CL = 4 CL = 5 (Burst type = interleave)(WR fine tune in code) -static const u16 CHB_DDR2_MRS_table[4] ={ 0x0150, 0x01D0, 0x0250, 0x02D0 }; // BL = 4; Use 1X-bandwidth MA table to init DRAM - -// MA11 MA10(AP) MA9 -#define CHB_MRS_DDR2_TWR2 (0 << 13) + (0 << 20) + (1 << 12) // Value = 001000h -#define CHB_MRS_DDR2_TWR3 (0 << 13) + (1 << 20) + (0 << 12) // Value = 100000h -#define CHB_MRS_DDR2_TWR4 (0 << 13) + (1 << 20) + (1 << 12) // Value = 101000h -#define CHB_MRS_DDR2_TWR5 (1 << 13) + (0 << 20) + (0 << 12) // Value = 002000h -#define CHB_MRS_DDR2_TWR6 (1 << 13) + (0 << 20) + (1 << 12) // Value = 003000h - -// DDR2 Twr = 2 Twr = 3 Twr = 4 Twr = 5 -static const u32 CHB_DDR2_Twr_table[5] = { CHB_MRS_DDR2_TWR2, CHB_MRS_DDR2_TWR3, CHB_MRS_DDR2_TWR4, CHB_MRS_DDR2_TWR5, CHB_MRS_DDR2_TWR6 }; - -#define CHB_OCD_Exit_150ohm 0x20200 | (1 << 20) // EMRS(1), BA0 = 1, MA9 = MA8 = MA7 = 0,MA6 = 1,MA2 = 0 (DRAM bus address) -// A17 = 1, A12 = A11 = A10 = 0,A9 = 1 ,A5 = 0 (CPU address) -#define CHB_OCD_Default_150ohm 0x21E00 | (1 << 20) // EMRS(1), BA0 = 1, MA9 = MA8 = MA7 = 1,MA6 = 1,MA2 = 0 (DRAM bus address) -// A17 = 1, A12 = A11 = A10 = 1,A9 = 1 ,A5 = 0 (CPU address) -//#define CHB_OCD_Exit_75ohm 0x20020 | (1 << 20) // EMRS(1), BA0 = 1, MA9 = MA8 = MA7 = 0,MA6 = 0,MA2 = 1 (DRAM bus address) -// A17 = 1, A12 = A11 = A10 = 0,A9 = 0 ,A5 = 1 (CPU address) -//#define CHB_OCD_Default_75ohm 0x21C20 | (1 << 20) // EMRS(1), BA0 = 1, MA9 = MA8 = MA7 = 1,MA6 = 0,MA2 = 1 (DRAM bus address) -// A17 = 1, A12 = A11 = A10 = 1,A9 = 0 ,A5 = 1 (CPU address) -void InitDDR2CHB( - DRAM_SYS_ATTR *DramAttr - ) - -{ - u8 Data; - u8 Idx, CL, BL, Twr; - u32 AccessAddr; - - Data = 0x80; - pci_write_config8(MEMCTRL, 0x54, Data); - - // step3. - //disable bank paging and multi page - Data = pci_read_config8(MEMCTRL, 0x69); - Data &= ~0x03; - pci_write_config8(MEMCTRL, 0x69, Data); - - Data = pci_read_config8(MEMCTRL, 0xd3); - Data |= 0x80; - pci_write_config8(MEMCTRL, 0xd3, Data); - - //step 4. Initialize CHB begin - Data = pci_read_config8(MEMCTRL, 0xd3); - Data |= 0x40; - pci_write_config8(MEMCTRL, 0xd3, Data); - - //Step 5. NOP command enable - Data = pci_read_config8(MEMCTRL, 0xd7); - Data &= 0xC7; - Data |= 0x08; - pci_write_config8(MEMCTRL, 0xd7, Data); - - //Step 6. issue a nop cycle,RegD3[7] 0 -> 1 - Data = pci_read_config8(MEMCTRL, 0xd3); - Data &= 0x7F; - pci_write_config8(MEMCTRL, 0xd3, Data); - Data |= 0x80; - pci_write_config8(MEMCTRL, 0xd3, Data); - - // Step 7. - // A minimum pause of 200u sec will be provided after the NOP. - // - <<< reduce BOOT UP time >>> - - // Loop 200us - for (Idx = 0; Idx < 0x10; Idx++) - WaitMicroSec(10); - - // Step 8. - // all banks precharge command enable - Data = pci_read_config8(MEMCTRL, 0xd7); - Data &= 0xC7; - Data |= 0x10; - pci_write_config8(MEMCTRL, 0xd7, Data); - - //step 9. issue a precharge all cycle,RegD3[7] 0 -> 1 - Data = pci_read_config8(MEMCTRL, 0xd3); - Data &= 0x7F; - pci_write_config8(MEMCTRL, 0xd3, Data); - Data |= 0x80; - pci_write_config8(MEMCTRL, 0xd3, Data); - - //step10. EMRS enable - Data = pci_read_config8(MEMCTRL, 0xd7); - Data &= 0xC7; - Data |= 0x18; - pci_write_config8(MEMCTRL, 0xd7, Data); - - Data = pci_read_config8(MEMCTRL, 0xd3); - Data &= 0xC7; - Data |= 0x08; - pci_write_config8(MEMCTRL, 0xd3, Data); - - //step11. EMRS DLL Enable and Disable DQS - AccessAddr = CHB_MRS_DLL_150[0] >> 3; - Data =(u8) (AccessAddr & 0xff); - pci_write_config8(MEMCTRL, 0xd9, Data); - - Data = (u8)((AccessAddr & 0xff00) >> 8); - pci_write_config8(MEMCTRL, 0xda, Data); - - Data = pci_read_config8(MEMCTRL, 0xd7); - Data &= 0xF9; - Data |= (u8)((AccessAddr & 0x30000) >> 15); - pci_write_config8(MEMCTRL, 0xd7, Data); - - //step12. issue EMRS cycle - Data = pci_read_config8(MEMCTRL, 0xd3); - Data &= 0x7F; - pci_write_config8(MEMCTRL, 0xd3, Data); - Data |= 0x80; - pci_write_config8(MEMCTRL, 0xd3, Data); - - //step13. MSR enable - Data = pci_read_config8(MEMCTRL, 0xd7); - Data &= 0xC7; - Data |= 0x18; - pci_write_config8(MEMCTRL, 0xd7, Data); - - Data = pci_read_config8(MEMCTRL, 0xd3); - Data &= 0xC7; - Data |= 0x00; - pci_write_config8(MEMCTRL, 0xd3, Data); - - //step 14. MSR DLL Reset - AccessAddr = CHB_MRS_DLL_150[1] >> 3; - Data =(u8) (AccessAddr & 0xff); - pci_write_config8(MEMCTRL, 0xd9, Data); - - Data = (u8)((AccessAddr & 0xff00) >> 8); - pci_write_config8(MEMCTRL, 0xda, Data); - - Data = pci_read_config8(MEMCTRL, 0xd7); - Data &= 0xF9; - Data |= (u8)((AccessAddr & 0x30000) >> 15); - pci_write_config8(MEMCTRL, 0xd7, Data); - - //step15. issue MRS cycle - Data = pci_read_config8(MEMCTRL, 0xd3); - Data &= 0x7F; - pci_write_config8(MEMCTRL, 0xd3, Data); - Data |= 0x80; - pci_write_config8(MEMCTRL, 0xd3, Data); - - //clear the address - Data = 0x00; - pci_write_config8(MEMCTRL, 0xda, Data); - - //step16. all banks precharge command enable - Data = pci_read_config8(MEMCTRL, 0xd7); - Data &= 0xC7; - Data |= 0x10; - pci_write_config8(MEMCTRL, 0xd7, Data); - - - // step17. issue precharge all cycle - Data = pci_read_config8(MEMCTRL, 0xd3); - Data &= 0x7F; - pci_write_config8(MEMCTRL, 0xd3, Data); - Data |= 0x80; - pci_write_config8(MEMCTRL, 0xd3, Data); - - //step18. CBR cycle enable - Data = pci_read_config8(MEMCTRL, 0xd7); - Data &= 0xC7; - Data |= 0x20; - pci_write_config8(MEMCTRL, 0xd7, Data); - - //step 19.20.21 - //repeat issue 8 CBR cycle, between each cycle stop 100us - for (Idx = 0; Idx < 8; Idx++) - { - // issue CBR cycle - Data = pci_read_config8(MEMCTRL, 0xd3); - Data &= 0x7F; - pci_write_config8(MEMCTRL, 0xd3, Data); - Data |= 0x80; - pci_write_config8(MEMCTRL, 0xd3, Data); - - WaitMicroSec(200); - } - - //step22. MSR enable - Data = pci_read_config8(MEMCTRL, 0xd7); - Data &= 0xC7; - Data |= 0x18; - pci_write_config8(MEMCTRL, 0xd7, Data); - - Data = pci_read_config8(MEMCTRL, 0xd3); - Data &= 0xC7; - Data |= 0x00; - pci_write_config8(MEMCTRL, 0xd3, Data); - - - //the SDRAM parameters.(Burst Length, CAS# Latency , Write recovery etc.) - //------------------------------------------------------------- - //Burst Length : really offset Rx6c[1] - Data = pci_read_config8(MEMCTRL, 0x6C); - BL = (Data & 0x02) >> 1; - - // CL = really offset RX62[2:0] - Data = pci_read_config8(MEMCTRL, 0x62); - CL = Data & 0x03; - - AccessAddr = (u32)(CHB_DDR2_MRS_table[CL]); - if (BL) - { - AccessAddr += 8; - } - - //Write recovery : really offset Rx63[7:5] - Data = pci_read_config8(MEMCTRL, 0x63); - Twr = (Data & 0xE0) >> 5; - - AccessAddr += CHB_DDR2_Twr_table[Twr]; - //MSR Address use addr[20:3] - AccessAddr >>= 3; - - //step 23. MSR command - Data = (u8)(AccessAddr & 0xFF); - pci_write_config8(MEMCTRL, 0xD9, Data); - - Data = (u8)((AccessAddr & 0xFF00) >> 8); - pci_write_config8(MEMCTRL, 0xda, Data); - - Data = pci_read_config8(MEMCTRL, 0xd7); - Data &= 0xF9; - Data |= (u8)(((AccessAddr & 0x30000)>>16) << 1); - pci_write_config8(MEMCTRL, 0xd7, Data); - - //step 24. issue MRS cycle - Data = pci_read_config8(MEMCTRL, 0xd3); - Data &= 0x7F; - pci_write_config8(MEMCTRL, 0xd3, Data); - Data |= 0x80; - pci_write_config8(MEMCTRL, 0xd3, Data); - - //step 25. EMRS enable - Data = pci_read_config8(MEMCTRL, 0xd7); - Data &= 0xC7; - Data |= 0x18; - pci_write_config8(MEMCTRL, 0xd7, Data); - - Data = pci_read_config8(MEMCTRL, 0xd3); - Data &= 0xC7; - Data |= 0x08; - pci_write_config8(MEMCTRL, 0xd3, Data); - - - //step 26. OCD default - AccessAddr = (CHB_OCD_Default_150ohm) >> 3; - Data =(u8) (AccessAddr & 0xff); - pci_write_config8(MEMCTRL, 0xd9, Data); - - Data = (u8)((AccessAddr & 0xff00) >> 8); - pci_write_config8(MEMCTRL, 0xda, Data); - - Data = pci_read_config8(MEMCTRL, 0xd7); - Data &= 0xF9; - Data |= (u8)((AccessAddr & 0x30000) >> 15); - pci_write_config8(MEMCTRL, 0xd7, Data); - - //step 27. issue EMRS cycle - Data = pci_read_config8(MEMCTRL, 0xd3); - Data &= 0x7F; - pci_write_config8(MEMCTRL, 0xd3, Data); - Data |= 0x80; - pci_write_config8(MEMCTRL, 0xd3, Data); - - //step 25. EMRS enable - Data = pci_read_config8(MEMCTRL, 0xd7); - Data &= 0xC7; - Data |= 0x18; - pci_write_config8(MEMCTRL, 0xd7, Data); - - Data = pci_read_config8(MEMCTRL, 0xd3); - Data &= 0xC7; - Data |= 0x08; - pci_write_config8(MEMCTRL, 0xd3, Data); - - //step 28. OCD Exit - AccessAddr = (CHB_OCD_Exit_150ohm) >> 3; - Data =(u8) (AccessAddr & 0xff); - pci_write_config8(MEMCTRL, 0xd9, Data); - - Data = (u8)((AccessAddr & 0xff00) >> 8); - pci_write_config8(MEMCTRL, 0xda, Data); - - Data = pci_read_config8(MEMCTRL, 0xd7); - Data &= 0xF9; - Data |= (u8)((AccessAddr & 0x30000) >> 15); - pci_write_config8(MEMCTRL, 0xd7, Data); - - //step 29. issue EMRS cycle - Data = pci_read_config8(MEMCTRL, 0xd3); - Data &= 0x7F; - pci_write_config8(MEMCTRL, 0xd3, Data); - Data |= 0x80; - pci_write_config8(MEMCTRL, 0xd3, Data); - - //clear all the address - Data = 0x00; - pci_write_config8(MEMCTRL, 0xd9, Data); - - Data = 0x00; - pci_write_config8(MEMCTRL, 0xda, Data); - - Data = pci_read_config8(MEMCTRL, 0xd7); - Data &= 0xF9; - pci_write_config8(MEMCTRL, 0xd7, Data); - - //step 30. normal SDRAM Mode - Data = pci_read_config8(MEMCTRL, 0xd7); - Data &= 0xC7; - Data |= 0x00; - pci_write_config8(MEMCTRL, 0xd7, Data); - - Data = pci_read_config8(MEMCTRL, 0xd3); - Data &= 0xC7; - Data |= 0x00; - pci_write_config8(MEMCTRL, 0xd3, Data); - - //step 31. exit the initialization mode - Data = pci_read_config8(MEMCTRL, 0xd3); - Data &= 0xBF; - pci_write_config8(MEMCTRL, 0xd3, Data); - - - //step 32. Enable bank paging and multi page - Data = pci_read_config8(MEMCTRL, 0x69); - Data |= 0x03; - pci_write_config8(MEMCTRL, 0x69, Data); -} -*/ - -/*=================================================================== Function : InitDDR2CHC() Precondition : Input : diff --git a/src/northbridge/via/vx800/dram_init.h b/src/northbridge/via/vx800/dram_init.h index e4e143aa0c..3e3f6aff98 100644 --- a/src/northbridge/via/vx800/dram_init.h +++ b/src/northbridge/via/vx800/dram_init.h @@ -33,7 +33,6 @@ //Dram Freq #define DIMMFREQ_800 400 #define DIMMFREQ_667 333 -//#define DIMMFREQ_600 300 #define DIMMFREQ_533 266 #define DIMMFREQ_400 200 #define DIMMFREQ_333 166 @@ -66,9 +65,7 @@ #define BURSTLENGTH4 4 //Data Width -//#define DATAWIDTHX16 16 -//#define DATAWIDTHX8 8 -//#define DATAWIDTHX4 4 + #define SPD_MEMORY_TYPE 2 /*Memory type FPM,EDO,SDRAM,DDR,DDR2 */ #define SPD_SDRAM_ROW_ADDR 3 /*Number of row addresses on this assembly */ @@ -133,17 +130,8 @@ typedef struct _DRAM_CONFIG_DATA { u8 CmdRate; u8 DualEn; - //u8 IntLv0; - //u8 IntLv1; - //u8 Ba0Sel; - //u8 Ba1Sel; - //u8 Ba2Sel; u8 BaScmb; u8 DrdyTiming; - //u8 Above4G; - //u8 RdsaitMode; - //u8 Rdsait; - //u8 TopPerf; u16 UMASize; } DRAM_CONFIG_DATA; diff --git a/src/northbridge/via/vx800/dram_util.c b/src/northbridge/via/vx800/dram_util.c index bb6498904f..31297b9030 100644 --- a/src/northbridge/via/vx800/dram_util.c +++ b/src/northbridge/via/vx800/dram_util.c @@ -182,7 +182,6 @@ void DumpRegisters(INTN DevNum, INTN FuncNum) u8 ByteVal; ByteVal = 0; - //pci_write_config8(PCI_DEV(0, DevNum, FuncNum), 0xA1, ByteVal); PRINT_DEBUG_MEM("\rDev %02x Fun %02x\r"); PRINT_DEBUG_MEM ("\r 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f\r"); diff --git a/src/northbridge/via/vx800/drdy_bl.c b/src/northbridge/via/vx800/drdy_bl.c index 0c5f63c2d4..73d897ace7 100644 --- a/src/northbridge/via/vx800/drdy_bl.c +++ b/src/northbridge/via/vx800/drdy_bl.c @@ -439,101 +439,12 @@ void DRAMDRDYSetting(DRAM_SYS_ATTR * DramAttr) Data |= 0x08; pci_write_config8(PCI_DEV(0, 0, 2), 0x54, Data); - //Data = pci_read_config8(PCI_DEV(0,0,2), 0x55); - //Data = Data & (~0x20); - //pci_write_config8(PCI_DEV(0,0,2), 0x55, Data); - //enable drdy timing Data = pci_read_config8(PCI_DEV(0, 0, 2), 0x51); Data = Data | 0x80; pci_write_config8(PCI_DEV(0, 0, 2), 0x51, Data); #endif -#if 0 //default - { - //disable drdy timing - Data = pci_read_config8(PCI_DEV(0, 0, 2), 0x51); - Data = Data & 0x7F; - pci_write_config8(PCI_DEV(0, 0, 2), 0x51, Data); - } -#endif -#if 0 // 2:Optimize - u8 CpuFreq, DramFreq; - u8 CL, RDRPH; - - //CL :reg6x[2:0] - Data = pci_read_config8(MEMCTRL, 0x62); - CL = Data & 0x07; - - //RDRPH: reg7B[6:4] - Data = pci_read_config8(MEMCTRL, 0x7B); - RDRPH = (Data & 0x70) >> 4; - - //CpuFreq: F2Reg54[7:5] - Data = pci_read_config8(PCI_DEV(0, 0, 2), 0x54); - CpuFreq = (Data & 0xE0) >> 5; - - //DramFreq:F3Reg90[2:0] - Data = pci_read_config8(MEMCTRL, 0x90); - DramFreq = Data & 0x07; - - u8 DelayMode; - DelayMode = CL + RDRPH; // RDELAYMD = bit0 of (CAS Latency + RDRPH) - DelayMode &= 0x01; - u8 ProgData[PT894_RDRDY_TBL_Width]; - - //In 364, there is no 128 bit - if (DelayMode == 1) { // DelayMode 1 - u8 Index; - for (Index = 0; Index < PT894_RDRDY_TBL_Width; Index++) - ProgData[Index] = - PT894_64bit_DELAYMD1_RCONV0[CpuFreq][DramFreq] - [Index]; - } else { // DelayMode 0 - u8 Index; - for (Index = 0; Index < PT894_RDRDY_TBL_Width; Index++) - ProgData[Index] = - PT894_64bit_DELAYMD0_RCONV0[CpuFreq][DramFreq] - [Index]; - } - - Data = ProgData[0]; - pci_write_config8(PCI_DEV(0, 0, 2), 0x60, Data); - - Data = ProgData[1]; - pci_write_config8(PCI_DEV(0, 0, 2), 0x61, Data); - - Data = ProgData[2]; - pci_write_config8(PCI_DEV(0, 0, 2), 0x62, Data); - - Data = ProgData[3]; - pci_write_config8(PCI_DEV(0, 0, 2), 0x63, Data); - - Data = ProgData[4]; - pci_write_config8(PCI_DEV(0, 0, 2), 0x64, Data); - - Data = ProgData[5]; - pci_write_config8(PCI_DEV(0, 0, 2), 0x65, Data); - - Data = ProgData[6]; - pci_write_config8(PCI_DEV(0, 0, 2), 0x66, Data); - - Data = ProgData[7]; - pci_write_config8(PCI_DEV(0, 0, 2), 0x67, Data); - - Data = pci_read_config8(PCI_DEV(0, 0, 2), 0x54); - Data = (Data & 0xF5) | ProgData[8]; - pci_write_config8(PCI_DEV(0, 0, 2), 0x54, Data); - - Data = pci_read_config8(PCI_DEV(0, 0, 2), 0x55); - Data = Data & (~0x22) | ProgData[9]; - pci_write_config8(PCI_DEV(0, 0, 2), 0x62, Data); - - //enable drdy timing - Data = pci_read_config8(PCI_DEV(0, 0, 2), 0x51); - Data = Data | 0x80; - pci_write_config8(PCI_DEV(0, 0, 2), 0x51, Data); -#endif } /*This routine process the ability for North Bridge side burst functionality diff --git a/src/northbridge/via/vx800/driving_clk_phase_data.h b/src/northbridge/via/vx800/driving_clk_phase_data.h index e9190fac30..b77c593e8f 100644 --- a/src/northbridge/via/vx800/driving_clk_phase_data.h +++ b/src/northbridge/via/vx800/driving_clk_phase_data.h @@ -16,51 +16,19 @@ #ifndef DRIVINGCLKPHASEDATA_H #define DRIVINGCLKPHASEDATA_H -//extern u8 DDR2_DQSA_Driving_Table[4]; -//extern u8 DDR2_DQSB_Driving_Table[2]; - -//extern u8 DDR2_DQA_Driving_Table[4]; -//extern u8 DDR2_DQB_Driving_Table[2]; - -//extern u8 DDR2_CSA_Driving_Table_x8[4]; -//extern u8 DDR2_CSB_Driving_Table_x8[2]; -//extern u8 DDR2_CSA_Driving_Table_x16[4]; -//extern u8 DDR2_CSB_Driving_Table_x16[2]; - #define MA_Table 3 -//extern u8 DDR2_MAA_Driving_Table[MA_Table][4]; -//extern u8 DDR2_MAB_Driving_Table[MA_Table][2]; - -//extern u8 DDR2_DCLKA_Driving_Table[4]; -//extern u8 DDR2_DCLKB_Driving_Table[4]; #define DUTY_CYCLE_FREQ_NUM 6 #define DUTY_CYCLE_REG_NUM 3 -//extern u8 ChA_Duty_Control_DDR2[DUTY_CYCLE_REG_NUM][DUTY_CYCLE_FREQ_NUM]; -//extern u8 ChB_Duty_Control_DDR2[DUTY_CYCLE_REG_NUM][DUTY_CYCLE_FREQ_NUM]; #define Clk_Phase_Table_DDR2_Width 6 -//extern u8 DDR2_ChA_Clk_Phase_Table_1R[3][Clk_Phase_Table_DDR2_Width]; -//extern u8 DDR2_ChB_Clk_Phase_Table_1R[3][Clk_Phase_Table_DDR2_Width]; -//extern u8 DDR2_ChA_Clk_Phase_Table_2R[3][Clk_Phase_Table_DDR2_Width]; #define WrtData_REG_NUM 4 #define WrtData_FREQ_NUM 6 -//extern u8 DDR2_ChA_WrtData_Phase_Table[WrtData_REG_NUM ][WrtData_FREQ_NUM]; -//extern u8 DDR2_ChB_WrtData_Phase_Table[WrtData_REG_NUM ][WrtData_FREQ_NUM]; #define DQ_DQS_Delay_Table_Width 4 -//extern u8 DDR2_CHA_DQ_DQS_Delay_Table[4][DQ_DQS_Delay_Table_Width]; -//extern u8 DDR2_CHB_DQ_DQS_Delay_Table[4][DQ_DQS_Delay_Table_Width]; #define DQS_INPUT_CAPTURE_REG_NUM 3 #define DQS_INPUT_CAPTURE_FREQ_NUM 6 -//extern u8 DDR2_ChA_DQS_Input_Capture_Tbl[DQS_INPUT_CAPTURE_REG_NUM ][DQS_INPUT_CAPTURE_FREQ_NUM]; -//extern u8 DDR2_ChB_DQS_Input_Capture_Tbl[DQS_INPUT_CAPTURE_REG_NUM ][DQS_INPUT_CAPTURE_FREQ_NUM]; - -//extern u8 Fixed_DQSA_1_2_Rank_Table[4][2]; -//extern u8 Fixed_DQSA_3_4_Rank_Table[4][2]; -//extern u8 Fixed_DQSB_1_2_Rank_Table[4][2]; -//extern u8 Fixed_DQSB_3_4_Rank_Table[4][2]; #endif /* DRIVINGCLKPHASEDATA_H */ diff --git a/src/northbridge/via/vx800/driving_setting.c b/src/northbridge/via/vx800/driving_setting.c index 95bae3cbab..a67c5b0e27 100644 --- a/src/northbridge/via/vx800/driving_setting.c +++ b/src/northbridge/via/vx800/driving_setting.c @@ -223,8 +223,6 @@ void DrivingODT(DRAM_SYS_ATTR * DramAttr) /*channel B */ if (1 == ENABLE_CHC) { //CHB has not auto compensation mode ,so must set it manual,or else CHB initialization will not successful - // Data =0x88; - //pci_write_config8(MEMCTRL, 0xd0, Data); Data = pci_read_config8(MEMCTRL, 0xd5); Data &= 0xAF; diff --git a/src/northbridge/via/vx800/early_serial.c b/src/northbridge/via/vx800/early_serial.c index 649339b353..8393aa79b1 100644 --- a/src/northbridge/via/vx800/early_serial.c +++ b/src/northbridge/via/vx800/early_serial.c @@ -54,9 +54,6 @@ void enable_vx800_serial(void) post_code(0x06); outb(0x03, 0x22); - //pci_write_config8(PCI_DEV(0,17,0),0xb4,0x7e); - //pci_write_config8(PCI_DEV(0,17,0),0xb0,0x10); - // turn on pnp vx800_writepnpaddr(0x87); vx800_writepnpaddr(0x87); diff --git a/src/northbridge/via/vx800/early_smbus.c b/src/northbridge/via/vx800/early_smbus.c index c7ef204b1e..fd03cfbd67 100644 --- a/src/northbridge/via/vx800/early_smbus.c +++ b/src/northbridge/via/vx800/early_smbus.c @@ -54,7 +54,6 @@ /* Internal functions */ static void smbus_print_error(unsigned char host_status_register, int loops) { -// printk(BIOS_ERR, "some i2c error\n"); /* Check if there actually was an error */ if (host_status_register == 0x00 || host_status_register == 0x40 || host_status_register == 0x42) diff --git a/src/northbridge/via/vx800/ide.c b/src/northbridge/via/vx800/ide.c index 3fb2c238e7..d2cdb5164a 100644 --- a/src/northbridge/via/vx800/ide.c +++ b/src/northbridge/via/vx800/ide.c @@ -172,7 +172,6 @@ static void ide_init(struct device *dev) for (i = 0; i < (16 * 12); i++) { pci_write_config8(dev, 0x40 + i, idedevicepcitable[i]); } - //pci_write_config8(dev, 0x0d, 0x20); data = pci_read_config8(dev, 0x0d); data &= 0x0f; data |= 0x40; @@ -185,59 +184,6 @@ static void ide_init(struct device *dev) /* Force interrupts to use compat mode. */ pci_write_config8(dev, PCI_INTERRUPT_PIN, 0x0); pci_write_config8(dev, PCI_INTERRUPT_LINE, 0xff); -#if 0 - u8 enables; - u32 cablesel; - - pci_write_config16(dev, 0x04, 0x0007); - - enables = pci_read_config8(dev, IDE_CS) & ~0x3; - enables |= 0x02; - pci_write_config8(dev, IDE_CS, enables); - enables = pci_read_config8(dev, IDE_CS); - printk(BIOS_DEBUG, "Enables in reg 0x40 read back as 0x%x\n", enables); - - /* Enable only compatibility mode. */ - enables = pci_read_config8(dev, IDE_CONF_II); - enables &= ~0xc0; - pci_write_config8(dev, IDE_CONF_II, enables); - enables = pci_read_config8(dev, IDE_CONF_II); - printk(BIOS_DEBUG, "Enables in reg 0x42 read back as 0x%x\n", enables); - - /* Enable prefetch buffers. */ - enables = pci_read_config8(dev, IDE_CONF_I); - enables |= 0xf0; - pci_write_config8(dev, IDE_CONF_I, enables); - - /* Flush FIFOs at half. */ - enables = pci_read_config8(dev, IDE_CONF_FIFO); - enables &= 0xf0; - enables |= (1 << 2) | (1 << 0); - pci_write_config8(dev, IDE_CONF_FIFO, enables); - - /* PIO read prefetch counter, Bus Master IDE Status Reg. Read Retry. */ - enables = pci_read_config8(dev, IDE_MISC_I); - enables &= 0xe2; - enables |= (1 << 4) | (1 << 3); - pci_write_config8(dev, IDE_MISC_I, enables); - - /* Use memory read multiple, Memory-Write-and-Invalidate. */ - enables = pci_read_config8(dev, IDE_MISC_II); - enables |= (1 << 2) | (1 << 3); - pci_write_config8(dev, IDE_MISC_II, enables); - - /* Force interrupts to use compat mode. */ - pci_write_config8(dev, PCI_INTERRUPT_PIN, 0x0); - pci_write_config8(dev, PCI_INTERRUPT_LINE, 0xff); - - /* Cable guy... */ - cablesel = pci_read_config32(dev, IDE_UDMA); - cablesel &= ~((1 << 28) | (1 << 20) | (1 << 12) | (1 << 4)); - cablesel |= (sb->ide0_80pin_cable << 28) | - (sb->ide0_80pin_cable << 20) | - (sb->ide1_80pin_cable << 12) | (sb->ide1_80pin_cable << 4); - pci_write_config32(dev, IDE_UDMA, cablesel); -#endif } static struct device_operations ide_ops = { diff --git a/src/northbridge/via/vx800/lpc.c b/src/northbridge/via/vx800/lpc.c index 427979646c..1ab11c05f7 100644 --- a/src/northbridge/via/vx800/lpc.c +++ b/src/northbridge/via/vx800/lpc.c @@ -83,11 +83,9 @@ static void pci_routing_fixup(struct device *dev) /* PCI slot */ printk(BIOS_INFO, "setting ide\n"); - //pci_assign_irqs(0, 0x0f, pin_to_irq(idePins)); /* Standard usb components */ printk(BIOS_INFO, "setting usb1-2\n"); -// pci_assign_irqs(0, 0x10, pin_to_irq(usbPins)); /* sound hardware */ printk(BIOS_INFO, "setting hdac audio\n"); @@ -109,7 +107,6 @@ static void setup_pm(device_t dev) pci_write_config8(dev, 0x82, 0x49); /* Primary interupt channel, define wake events 0 = IRQ0 15 = IRQ15 1 = en. */ -// pci_write_config16(dev, 0x84, 0x30f2); pci_write_config16(dev, 0x84, 0x609a); // 0x609a?? /* SMI output level to low, 7.5us throttle clock */ @@ -131,8 +128,6 @@ static void setup_pm(device_t dev) /* GP2 Timer Counter */ pci_write_config8(dev, 0x99, 0xfb); - /* GP3 Timer Counter */ - //pci_write_config8(dev, 0x9a, 0x20); /* Multi Function Select 1 */ pci_write_config8(dev, 0xe4, 0x00); @@ -178,16 +173,6 @@ static void setup_pm(device_t dev) * Will work for C3 and for FID/VID change. */ outb(0x1, VX800_ACPI_IO_BASE + 0x11); -/* - outw(0x0, 0x424); - outw(0x0, 0x42a); - outw(0x1, 0x42c); - outl(0x0, 0x434); - outl(0x01, 0x438); - outb(0x0, 0x442); - outl(0xffff7fff, 0x448); - outw(0x001, 0x404); -*/ } static void S3_ps2_kb_ms_wakeup(struct device *dev) @@ -234,7 +219,6 @@ static void vx800_sb_init(struct device *dev) pci_write_config8(dev, 0x6C, enables); // Map 4MB of FLASH into the address space -// pci_write_config8(dev, 0x41, 0x7f); // Set bit 6 of 0x40, because Award does it (IO recovery time) // IMPORTANT FIX - EISA 0x4d0 decoding must be on so that PCI @@ -255,7 +239,6 @@ static void vx800_sb_init(struct device *dev) pci_write_config8(dev, 0x59, 0x80); /* Set 0x5b to 0x01 to match Award */ - //pci_write_config8(dev, 0x5b, 0x01); enables = pci_read_config8(dev, 0x5b); enables |= 0x01; pci_write_config8(dev, 0x5b, enables); @@ -264,7 +247,6 @@ static void vx800_sb_init(struct device *dev) pci_write_config8(dev, 0x48, 0x0c); /* Set 0x58 to 0x42 APIC and RTC. */ - //pci_write_config8(dev, 0x58, 0x42); this cmd cause the irq0 can not be triggerd,since bit 5 was set to 0. enables = pci_read_config8(dev, 0x58); enables |= 0x41; // pci_write_config8(dev, 0x58, enables); diff --git a/src/northbridge/via/vx800/northbridge.c b/src/northbridge/via/vx800/northbridge.c index 639132132f..e6ec3b5087 100644 --- a/src/northbridge/via/vx800/northbridge.c +++ b/src/northbridge/via/vx800/northbridge.c @@ -38,22 +38,6 @@ static void memctrl_init(device_t dev) /* set VGA in uma_ram_setting.c, not in this function. */ -#if 0 - pci_write_config8(dev, 0x85, 0x20); - pci_write_config8(dev, 0x86, 0x2d); - - /* Set up VGA timers */ - pci_write_config8(dev, 0xa2, 0x44); - - /* Enable VGA with a 32mb framebuffer */ - pci_write_config16(dev, 0xa0, 0xd000); - - pci_write_config16(dev, 0xa4, 0x0010); - - //b0: 60 aa aa 5a 0f 00 00 00 08 - pci_write_config16(dev, 0xb0, 0xaa00); - pci_write_config8(dev, 0xb8, 0x08); -#endif } static const struct device_operations memctrl_operations = { diff --git a/src/northbridge/via/vx800/rank_map.c b/src/northbridge/via/vx800/rank_map.c index 069257c660..5c9b0ad366 100644 --- a/src/northbridge/via/vx800/rank_map.c +++ b/src/northbridge/via/vx800/rank_map.c @@ -91,7 +91,6 @@ void DRAMSizingMATypeM(DRAM_SYS_ATTR * DramAttr) { DRAMClearEndingAddress(DramAttr); DRAMSizingEachRank(DramAttr); - //DRAMReInitDIMMBL (DramAttr); DRAMSetRankMAType(DramAttr); DRAMSetEndingAddress(DramAttr); DRAMPRToVRMapping(DramAttr); diff --git a/src/northbridge/via/vx800/uma_ram_setting.c b/src/northbridge/via/vx800/uma_ram_setting.c index bf5909316a..46c2782d1a 100644 --- a/src/northbridge/via/vx800/uma_ram_setting.c +++ b/src/northbridge/via/vx800/uma_ram_setting.c @@ -94,23 +94,16 @@ void SetUMARam(void) //GMINT and GFX relatate //note Bit 3 VGA Enable pci_write_config8(MEMCTRL, 0xa7, 0x8c); - // ByteVal = 0x4c; //GMINT Misc.1 - //pci_write_config8(MEMCTRL, 0xb0, 0x80); - - //pci_write_config8(MEMCTRL, 0xb1, 0xaa); //AGPCINT MISC - //pci_write_config8(MEMCTRL, 0xb2, 0x82); - //ByteVal = 0x8A; //GMINT MISC.2 //disable read pass write pci_write_config8(MEMCTRL, 0xb3, 0x9A); //EPLL Register - //pci_write_config8(MEMCTRL, 0xb4, 0x04); //enable CHA and CHB merge mode pci_write_config8(MEMCTRL, 0xde, 0x06); @@ -133,17 +126,12 @@ void SetUMARam(void) ByteVal = (ByteVal & 0x8f) | (SLD0F3Val << 4); pci_write_config8(MEMCTRL, 0xa1, ByteVal); -// vga_dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VX855_VGA, 0); - //RxB2 may be for S.L. and RxB1 may be for L. L. // It is different from Spec. ByteVal = SLD1F0Val; pci_write_config8(vga_dev, 0xb2, ByteVal); //set M1 size - //ByteVal = pci_read_config8(MEMCTRL, 0xa3); - //ByteVal = 0x02; - //pci_write_config8(MEMCTRL, 0xa3, ByteVal); PRINT_DEBUG_MEM("UMA setting - 3\n"); @@ -177,7 +165,6 @@ void SetUMARam(void) //enable GFx memory space access control for S.L and mmio ByteVal = pci_read_config8(d0f0_dev, 0xD4); ByteVal |= 0x03; - //ByteVal |= 0x01; pci_write_config8(d0f0_dev, 0xD4, ByteVal); //enable Base VGA 16 Bits Decode @@ -189,15 +176,12 @@ void SetUMARam(void) //set VGA memory selection ByteVal = pci_read_config8(vga_dev, 0xb0); ByteVal &= 0xF8; - //ByteVal |= 0x01; ByteVal |= 0x03; pci_write_config8(vga_dev, 0xb0, ByteVal); //set LL size //enable memory access to SL,MMIO,LL and IO to 3B0~3BB,3C0 ~3DF - //ByteVal = 0x03; - //pci_write_config8(d0f0_dev, 0xc0, ByteVal); //Turn on Graphic chip IO port port access ByteVal = inb(0x03C3); @@ -216,9 +200,6 @@ void SetUMARam(void) ByteVal = inb(0x03CC); ByteVal |= 0x03; outb(ByteVal, 0x03C2); - // ByteVal = inb(0x03C2); - // ByteVal |= 0x01; - // outb(ByteVal,0x03C2); #if 1 //bios porting guide has no this two defination: 3d on 3d4/3d5 and 39 on 3c4/3c5 //set frequence 0x3D5.3d[7:4] @@ -329,101 +310,8 @@ void SetUMARam(void) ByteVal = (ByteVal & 0xE5) | 0x1A; outb(ByteVal, 0x03d5); -#if 0 - u8 table3c43c5[0x70] = { - 0x03, 0x01, 0x0F, 0x00, 0x06, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x01, 0x78, 0x00, 0x00, 0x00, 0xBE, 0x20, 0x7F, - 0x60, 0x7F, 0x08, 0x31, 0xCC, 0x00, 0x01, 0x00, - 0x00, 0x18, 0x10, 0x00, 0x00, 0x00, 0x3D, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x04, 0xF3, 0xFF, 0xFC, - 0xF8, 0x0C, 0x00, 0x00, 0x40, 0x06, 0x11, 0x22, - 0x51, 0x10, 0x00, 0x01, 0x19, 0x0C, 0x00, 0xFF, - 0x38, 0x40, 0x30, 0xFF, 0x70, 0x8C, 0x85, 0x9D, - 0x80, 0x05, 0x54, 0x90, 0x03, 0x30, 0x00, 0x5F, - 0x1F, 0x00, 0x00, 0xFF, 0x00, 0x00, 0xFF, 0x00, - 0x06, 0xDF, 0x00, 0x20, 0x20, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x40, 0x20, 0x00, 0x20, 0x20, - 0xE0, 0x20, 0xD0, 0x3F, 0x00, 0xE0, 0x00, 0x00 - }; - u8 table3d43d5[0x88] = { - 0x7F, 0x63, 0x63, 0x83, 0x69, 0x19, 0x72, 0xE0, - 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x58, 0x9C, 0x57, 0x90, 0x00, 0x57, 0x73, 0xE3, - 0x57, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x0C, 0x00, 0x11, 0x06, 0x00, 0x20, 0x01, 0x34, - 0xEE, 0x74, 0x01, 0x01, 0x08, 0x84, 0x00, 0x00, - 0x00, 0xF3, 0x40, 0x90, 0x00, 0x00, 0x00, 0x01, - 0x00, 0x12, 0x00, 0x02, 0x00, 0x00, 0x10, 0x00, - 0x9D, 0x9D, 0x9D, 0x9D, 0x9D, 0x9D, 0x9D, 0x9D, - 0x9D, 0x9D, 0x9D, 0x9D, 0x9D, 0x9D, 0x9D, 0x9D, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x9D, 0x9D, 0x10, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x9D, 0x9D, 0x9D, - 0x9D, 0x9D, 0x9D, 0x9D, 0x00, 0x9D, 0x1D, 0x00, - 0x00, 0x00, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, - 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, - }; - - u8 table3c0space[0xc0] = { - 0x11, 0x00, 0x10, 0x01, 0x26, 0x3D, 0xFF, 0x00, - 0x10, 0x3F, 0x00, 0x00, 0x2F, 0x00, 0x22, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x50, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - }; - - //for (i = 0;i < 0xc0;i++) - for (i = 0; i < 0x40; i++) - { - outb(table3c0space[i], 0x03c0 + i); - } - - for (i = 0; i < 0x70; i++) { - outb(i, 0x03c4); - outb(table3c43c5[i], 0x03c5); - } - for (i = 0; i < 0x88; i++) { - outb(i, 0x03d4); - outb(table3d43d5[i], 0x03d5); - } - - outb(0x92, 0x03d4); - outb(0x80, 0x03d5); - - outb(0xa3, 0x03d4); - outb(0x00, 0x03d5); - - outb(0xe8, 0x03d4); - outb(0x40, 0x03d5); -#endif - // 3d4 3d freq // IO Port / Index: 3X5.3D // Scratch Pad Register 4 -// outb(0x39,0x03c4); -// outb(1 << SLD0F3Val ,0x03c5); -// #endif - } diff --git a/src/northbridge/via/vx800/vga.c b/src/northbridge/via/vx800/vga.c index 664e91583a..70a916f195 100644 --- a/src/northbridge/via/vx800/vga.c +++ b/src/northbridge/via/vx800/vga.c @@ -134,10 +134,6 @@ static void write_protect_vgabios(void) PCI_DEVICE_ID_VIA_VX855_MEMCTRL, 0); if (dev) pci_write_config8(dev, 0x80, 0xff); - /*vx855 no th 0x61 reg */ - /*dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VX855_VLINK, 0); - //if (dev) - // pci_write_config8(dev, 0x61, 0xff); */ } #endif @@ -166,15 +162,6 @@ static void vga_init(device_t dev) reg8 = reg8 | 2; outb(reg8, 0x92); - //* - //pci_write_config8(dev, 0x04, 0x07); - //pci_write_config32(dev,0x10, 0xa0000008); - //pci_write_config32(dev,0x14, 0xdd000000); - pci_write_config32(dev, 0x10, VIACONFIG_VGA_PCI_10); - pci_write_config32(dev, 0x14, VIACONFIG_VGA_PCI_14); - pci_write_config8(dev, 0x3c, 0x0a); //same with vx855_lpc.c - //*/ - printk(BIOS_DEBUG, "Initializing VGA...\n"); pci_dev_init(dev); @@ -192,13 +179,6 @@ static void vga_init(device_t dev) reg8 |= (0x3 << 4); outb(0x3d, CRTM_INDEX); outb(reg8, CRTM_DATA); - -#if 0 - /* Set framebuffer size to CONFIG_VIDEO_MB mb */ - reg8 = (CONFIG_VIDEO_MB/4); - outb(0x39, SR_INDEX); - outb(reg8, SR_DATA); -#endif } } diff --git a/src/northbridge/via/vx800/vx800.h b/src/northbridge/via/vx800/vx800.h index c9ae130982..d2eb46f5e2 100644 --- a/src/northbridge/via/vx800/vx800.h +++ b/src/northbridge/via/vx800/vx800.h @@ -26,12 +26,9 @@ void smbus_fixup(const struct mem_controller *mem_ctrl); void enable_vx800_serial(void); #endif -//#define REV_B0 0x10 #define REV_B1 0x11 -//#define REV_B2 0x12 #define REV_B3 0x13 #define REV_B4 0x14 -//#define REV_B2 0xB4 #define REV_B0 0x00 #define REV_B2 0x01 diff --git a/src/northbridge/via/vx900/chrome9hd.c b/src/northbridge/via/vx900/chrome9hd.c index 03c8e0cf55..c99f10e889 100644 --- a/src/northbridge/via/vx900/chrome9hd.c +++ b/src/northbridge/via/vx900/chrome9hd.c @@ -306,7 +306,6 @@ static void chrome9hd_init(device_t dev) vga_misc_mask(1 << 0, 1 << 0); /* FIXME: recheck; Enable Base VGA 16 Bits Decode */ - ////pci_mod_config8(host, 0x4e, 0, 1<<4); u32 fb_address = pci_read_config32(dev, PCI_BASE_ADDRESS_2); fb_address &= ~0x0F; diff --git a/src/northbridge/via/vx900/lpc.c b/src/northbridge/via/vx900/lpc.c index 4f3d704a8c..a9d24df91f 100644 --- a/src/northbridge/via/vx900/lpc.c +++ b/src/northbridge/via/vx900/lpc.c @@ -77,7 +77,7 @@ static void vx900_lpc_dma_setup(device_t dev) /* Enable Positive South Module PCI Cycle Decoding */ /* FIXME: Setting this seems to hang our system */ - //pci_mod_config8(dev, 0x58, 0, 1<<4); + /* Positive decoding for ROM + APIC + On-board IO ports */ pci_mod_config8(dev, 0x6c, 0, (1 << 2) | (1 << 3) | (1 << 7)); /* Enable DMA channels. BIOS guide recommends DMA channel 2 off */ diff --git a/src/northbridge/via/vx900/raminit_ddr3.c b/src/northbridge/via/vx900/raminit_ddr3.c index aff62f2773..4878571742 100644 --- a/src/northbridge/via/vx900/raminit_ddr3.c +++ b/src/northbridge/via/vx900/raminit_ddr3.c @@ -326,9 +326,8 @@ static void vx900_dram_write_init_config(void) /* Fast cycle control for CPU-to-DRAM Read Cycle 0:Disabled. * This CPU bus controller will wait for all data */ - ////pci_mod_config8(HOST_BUS, 0x51, (1 << 7), 0); + /* Memory to CPU bus Controller Conversion Mode 1: Synchronous mode */ - ////pci_mod_config8(HOST_BUS, 0x54, 0, (1 << 1)); } static void dram_find_spds_ddr3(const dimm_layout * addr, dimm_info * dimm) @@ -1335,7 +1334,6 @@ static void vx900_dram_calibrate_transmit_delays(delay_range * tx_dq, /* FIXME: Except that we have not yet told the MCU what * the geometry of the DIMM is, hence we don't trust * this test for now */ - ////continue; } /* Good. We should be able to use this DIMM */ /* That's it. We're done */ @@ -1614,14 +1612,8 @@ static void vx900_dram_write_final_config(ramctr_timing * ctrl) /* Tri-state MCSi# when rank is in self-refresh */ pci_mod_config8(MCU, 0x99, 0, 0x0f); - ////pci_write_config8(MCU, 0x69, 0xe7); /* Enable paging mode and 8 page registers */ pci_mod_config8(MCU, 0x69, 0, 0xe5); - ////pci_write_config8(MCU, 0x72, 0x0f); - - ////pci_write_config8(MCU, 0x97, 0xa4); /* self-refresh */ - ////pci_write_config8(MCU, 0x98, 0xba); /* self-refresh II */ - ////pci_write_config8(MCU, 0x9a, 0x80); /* self-refresh III */ /* Enable automatic triggering of short ZQ calibration */ pci_write_config8(MCU, 0xc8, 0x80); |