diff options
| -rw-r--r-- | src/mainboard/system76/adl/variants/darp8/overridetree.cb | 13 | ||||
| -rw-r--r-- | src/mainboard/system76/adl/variants/lemp11/overridetree.cb | 13 |
2 files changed, 14 insertions, 12 deletions
diff --git a/src/mainboard/system76/adl/variants/darp8/overridetree.cb b/src/mainboard/system76/adl/variants/darp8/overridetree.cb index 91b029111a..1feac2b916 100644 --- a/src/mainboard/system76/adl/variants/darp8/overridetree.cb +++ b/src/mainboard/system76/adl/variants/darp8/overridetree.cb @@ -151,12 +151,13 @@ chip soc/intel/alderlake .clk_req = 4, .flags = PCIE_RP_LTR, }" - chip soc/intel/common/block/pcie/rtd3 - register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D16)" # SSD1_PWR_EN - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B16)" # M2_SSD1_RST# - register "srcclk_pin" = "4" # SSD1_CLKREQ# - device generic 0 on end - end + # FIXME: Drives do not exit D3cold on S3 exit + #chip soc/intel/common/block/pcie/rtd3 + # register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D16)" # SSD1_PWR_EN + # register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B16)" # M2_SSD1_RST# + # register "srcclk_pin" = "4" # SSD1_CLKREQ# + # device generic 0 on end + #end end device ref pmc hidden chip drivers/intel/pmc_mux diff --git a/src/mainboard/system76/adl/variants/lemp11/overridetree.cb b/src/mainboard/system76/adl/variants/lemp11/overridetree.cb index 379dad8bb3..34e8041269 100644 --- a/src/mainboard/system76/adl/variants/lemp11/overridetree.cb +++ b/src/mainboard/system76/adl/variants/lemp11/overridetree.cb @@ -137,12 +137,13 @@ chip soc/intel/alderlake .clk_req = 1, .flags = PCIE_RP_LTR, }" - chip soc/intel/common/block/pcie/rtd3 - register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D16)" # SSD1_PWR_EN - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H0)" # M2_SSD1_RST# - register "srcclk_pin" = "1" # SSD1_CLKREQ# - device generic 0 on end - end + # FIXME: Drives do not exit D3cold on S3 exit + #chip soc/intel/common/block/pcie/rtd3 + # register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D16)" # SSD1_PWR_EN + # register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H0)" # M2_SSD1_RST# + # register "srcclk_pin" = "1" # SSD1_CLKREQ# + # device generic 0 on end + #end end device ref pmc hidden chip drivers/intel/pmc_mux |