diff options
| -rw-r--r-- | src/cpu/intel/Kconfig | 1 | ||||
| -rw-r--r-- | src/cpu/intel/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/cpu/intel/slot_1/Kconfig | 33 | ||||
| -rw-r--r-- | src/cpu/intel/slot_1/Makefile.inc | 29 | ||||
| -rw-r--r-- | src/cpu/intel/slot_1/chip.h | 24 | ||||
| -rw-r--r-- | src/cpu/intel/slot_1/slot_1.c | 26 |
6 files changed, 114 insertions, 0 deletions
diff --git a/src/cpu/intel/Kconfig b/src/cpu/intel/Kconfig index 24a9b4d9c4..3e38e477ad 100644 --- a/src/cpu/intel/Kconfig +++ b/src/cpu/intel/Kconfig @@ -8,6 +8,7 @@ source src/cpu/intel/model_106cx/Kconfig source src/cpu/intel/bga956/Kconfig source src/cpu/intel/ep80579/Kconfig source src/cpu/intel/slot_2/Kconfig +source src/cpu/intel/slot_1/Kconfig source src/cpu/intel/socket_mFCPGA478/Kconfig source src/cpu/intel/socket_mPGA478/Kconfig source src/cpu/intel/socket_mPGA479M/Kconfig diff --git a/src/cpu/intel/Makefile.inc b/src/cpu/intel/Makefile.inc index f5de4b8090..c94b56ff31 100644 --- a/src/cpu/intel/Makefile.inc +++ b/src/cpu/intel/Makefile.inc @@ -13,6 +13,7 @@ subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA603) += socket_mPGA603 subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA604) += socket_mPGA604 subdirs-$(CONFIG_CPU_INTEL_SOCKET_PGA370) += socket_PGA370 subdirs-$(CONFIG_CPU_INTEL_SLOT_2) += slot_2 +subdirs-$(CONFIG_CPU_INTEL_SLOT_1) += slot_1 #socket_mPGA604_533Mhz #socket_mPGA604_800Mhz diff --git a/src/cpu/intel/slot_1/Kconfig b/src/cpu/intel/slot_1/Kconfig new file mode 100644 index 0000000000..31eea999a6 --- /dev/null +++ b/src/cpu/intel/slot_1/Kconfig @@ -0,0 +1,33 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2010 Keith Hui <buurin@gmail.com> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +config CPU_INTEL_SLOT_1 + bool + +config DCACHE_RAM_BASE + hex + default 0xc0000 + depends on CPU_INTEL_SLOT_1 + +config DCACHE_RAM_SIZE + hex + default 0x01000 + depends on CPU_INTEL_SLOT_1 + diff --git a/src/cpu/intel/slot_1/Makefile.inc b/src/cpu/intel/slot_1/Makefile.inc new file mode 100644 index 0000000000..169265664c --- /dev/null +++ b/src/cpu/intel/slot_1/Makefile.inc @@ -0,0 +1,29 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +obj-y += slot_1.o +subdirs-y += ../model_6xx +subdirs-y += ../../x86/tsc +subdirs-y += ../../x86/mtrr +subdirs-y += ../../x86/lapic +subdirs-y += ../../x86/cache +subdirs-y += ../../x86/smm +subdirs-y += ../microcode + diff --git a/src/cpu/intel/slot_1/chip.h b/src/cpu/intel/slot_1/chip.h new file mode 100644 index 0000000000..6721d6ee8b --- /dev/null +++ b/src/cpu/intel/slot_1/chip.h @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Keith Hui <buurin@gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations cpu_intel_slot_1_ops; + +struct cpu_intel_slot_1_config { +}; diff --git a/src/cpu/intel/slot_1/slot_1.c b/src/cpu/intel/slot_1/slot_1.c new file mode 100644 index 0000000000..548127fbcc --- /dev/null +++ b/src/cpu/intel/slot_1/slot_1.c @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Keith Hui <buurin@gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/device.h> +#include "chip.h" + +struct chip_operations cpu_intel_slot_1_ops = { + CHIP_NAME("Slot 1 CPU") +}; |