diff options
| -rw-r--r-- | src/drivers/generic/bayhub_lv2/lv2.c | 8 | ||||
| -rw-r--r-- | src/drivers/generic/bayhub_lv2/lv2.h | 7 |
2 files changed, 1 insertions, 14 deletions
diff --git a/src/drivers/generic/bayhub_lv2/lv2.c b/src/drivers/generic/bayhub_lv2/lv2.c index 814cfb69c9..90e1e5d105 100644 --- a/src/drivers/generic/bayhub_lv2/lv2.c +++ b/src/drivers/generic/bayhub_lv2/lv2.c @@ -28,21 +28,15 @@ static void lv2_enable(struct device *dev) pci_update_config32(dev, LV2_PCR_HEX_FC, LV2_ASPM_L1_TIMER_MASK, LV2_ASPM_L1_TIMER); pci_or_config32(dev, LV2_PCR_HEX_A8, LV2_LTR_ENABLE); pci_write_config32(dev, LV2_PCR_HEX_234, LV2_MAX_LATENCY_SETTING); - pci_update_config32(dev, LV2_PCR_HEX_248, LV2_L1_SUBSTATE_SETTING_MASK, - LV2_L1_SUBSTATE_SETTING); pci_update_config32(dev, LV2_PCR_HEX_3F4, LV2_L1_SUBSTATE_OPTIMISE_MASK, LV2_L1_SUBSTATE_OPTIMISE); - pci_or_config32(dev, LV2_LINK_CTRL, LV2_LINK_CTRL_CLKREQ); pci_update_config32(dev, LV2_PCR_HEX_300, LV2_TUNING_WINDOW_MASK, LV2_TUNING_WINDOW); pci_update_config32(dev, LV2_PCR_HEX_304, LV2_DRIVER_STRENGTH_MASK, LV2_DRIVER_STRENGTH); pci_update_config32(dev, LV2_PCR_HEX_308, LV2_RESET_DMA_DISABLE_MASK, LV2_RESET_DMA_DISABLE); - pci_update_config32(dev, LV2_LINK_CTRL, LV2_LINK_CTRL_L1_L0_MASK, - LV2_LINK_CTRL_L1_ENABLE); pci_write_config32(dev, LV2_PROTECT, LV2_PROTECT_ON | LV2_PROTECT_LOCK_ON); - printk(BIOS_INFO, "BayHub LV2: Power-saving enabled (link_ctrl=%#x)\n", - pci_read_config32(dev, LV2_LINK_CTRL)); + printk(BIOS_INFO, "BayHub LV2: Power-saving enabled\n"); } static struct device_operations lv2_ops = { diff --git a/src/drivers/generic/bayhub_lv2/lv2.h b/src/drivers/generic/bayhub_lv2/lv2.h index 464fed8ac0..9eef4b3fc3 100644 --- a/src/drivers/generic/bayhub_lv2/lv2.h +++ b/src/drivers/generic/bayhub_lv2/lv2.h @@ -21,9 +21,6 @@ enum { LV2_PCI_PM_L1_TIMER_MASK = 0x0FFFFFFF, LV2_PCR_HEX_234 = 0x234, LV2_MAX_LATENCY_SETTING = 0x10011001, - LV2_PCR_HEX_248 = 0x248, - LV2_L1_SUBSTATE_SETTING = 0x0000000A, - LV2_L1_SUBSTATE_SETTING_MASK = 0xFFFFFFF0, LV2_PCR_HEX_3F4 = 0x3F4, LV2_L1_SUBSTATE_OPTIMISE = 0x0000000A, LV2_L1_SUBSTATE_OPTIMISE_MASK = 0xFFFFFFF0, @@ -36,8 +33,4 @@ enum { LV2_PCR_HEX_308 = 0x308, LV2_RESET_DMA_DISABLE = 0x00C00000, LV2_RESET_DMA_DISABLE_MASK = 0xFF3FFFFF, - LV2_LINK_CTRL = 0x90, - LV2_LINK_CTRL_L1_ENABLE = BIT(1), - LV2_LINK_CTRL_L1_L0_MASK = 0xFFFFFFFC, - LV2_LINK_CTRL_CLKREQ = BIT(8), }; |