diff options
| -rw-r--r-- | src/soc/qualcomm/sc7180/qupv3_config.c | 5 | ||||
| -rw-r--r-- | src/soc/qualcomm/sc7180/qupv3_uart.c | 4 |
2 files changed, 3 insertions, 6 deletions
diff --git a/src/soc/qualcomm/sc7180/qupv3_config.c b/src/soc/qualcomm/sc7180/qupv3_config.c index b5adee2b7c..3dbe3e67cb 100644 --- a/src/soc/qualcomm/sc7180/qupv3_config.c +++ b/src/soc/qualcomm/sc7180/qupv3_config.c @@ -54,10 +54,7 @@ void qupv3_se_fw_load_and_init(unsigned int bus, unsigned int protocol, /* HPG section 3.1.7.1 */ - if (protocol == SE_PROTOCOL_UART) { - /* To maintain Div=4 for QcLib, configure clock to 7372800Hz for sc7180 */ - clock_configure_qup(bus, QUPV3_UART_SRC_HZ); - } else { + if (protocol != SE_PROTOCOL_UART) { setbits_le32(®s->geni_dfs_if_cfg, GENI_DFS_IF_CFG_DFS_IF_EN_BMSK); /* configure clock dfsr */ diff --git a/src/soc/qualcomm/sc7180/qupv3_uart.c b/src/soc/qualcomm/sc7180/qupv3_uart.c index bf274c23c9..45d3d02d58 100644 --- a/src/soc/qualcomm/sc7180/qupv3_uart.c +++ b/src/soc/qualcomm/sc7180/qupv3_uart.c @@ -71,7 +71,7 @@ void uart_init(unsigned int idx) /* sc7180 requires 16 clock pulses to sample 1 bit of data */ uart_freq = baud_rate * 16; - div = DIV_ROUND_CLOSEST(QUPV3_UART_SRC_HZ, uart_freq); + div = DIV_ROUND_CLOSEST(SRC_XO_HZ, uart_freq); write32(®s->geni_ser_m_clk_cfg, (div << 4) | 1); write32(®s->geni_ser_s_clk_cfg, (div << 4) | 1); @@ -147,7 +147,7 @@ void uart_fill_lb(void *data) serial.baseaddr = (uint32_t)uart_platform_base(CONFIG_UART_FOR_CONSOLE); serial.baud = get_uart_baudrate(); serial.regwidth = 4; - serial.input_hertz = QUPV3_UART_SRC_HZ; + serial.input_hertz = SRC_XO_HZ; lb_add_serial(&serial, data); } |