diff options
| -rw-r--r-- | src/soc/intel/elkhartlake/include/soc/pci_devs.h | 82 |
1 files changed, 82 insertions, 0 deletions
diff --git a/src/soc/intel/elkhartlake/include/soc/pci_devs.h b/src/soc/intel/elkhartlake/include/soc/pci_devs.h index 659de21ebd..8cf193829c 100644 --- a/src/soc/intel/elkhartlake/include/soc/pci_devs.h +++ b/src/soc/intel/elkhartlake/include/soc/pci_devs.h @@ -47,6 +47,24 @@ #define PCH_DEV_I2C7 _PCH_DEV(IEH, 1) #define PCH_DEV_IEH _PCH_DEV(IEH, 5) +#define PCH_DEV_SLOT_PSE0 0x11 +#define PCH_DEVFN_PSEUART0 _PCH_DEVFN(PSE0, 0) +#define PCH_DEVFN_PSEUART1 _PCH_DEVFN(PSE0, 1) +#define PCH_DEVFN_PSEUART2 _PCH_DEVFN(PSE0, 2) +#define PCH_DEVFN_PSEUART3 _PCH_DEVFN(PSE0, 3) +#define PCH_DEVFN_PSEUART4 _PCH_DEVFN(PSE0, 4) +#define PCH_DEVFN_PSEUART5 _PCH_DEVFN(PSE0, 5) +#define PCH_DEVFN_PSEIS20 _PCH_DEVFN(PSE0, 6) +#define PCH_DEVFN_PSEIS21 _PCH_DEVFN(PSE0, 7) +#define PCH_DEV_PSEUART0 _PCH_DEV(PSE0, 0) +#define PCH_DEV_PSEUART1 _PCH_DEV(PSE0, 1) +#define PCH_DEV_PSEUART2 _PCH_DEV(PSE0, 2) +#define PCH_DEV_PSEUART3 _PCH_DEV(PSE0, 3) +#define PCH_DEV_PSEUART4 _PCH_DEV(PSE0, 4) +#define PCH_DEV_PSEUART5 _PCH_DEV(PSE0, 5) +#define PCH_DEV_PSEIS20 _PCH_DEV(PSE0, 6) +#define PCH_DEV_PSEIS21 _PCH_DEV(PSE0, 7) + #define PCH_DEV_SLOT_SIO0 0x12 #define PCH_DEVFN_GSPI2 _PCH_DEVFN(SIO0, 0) #define PCH_DEVFN_CSE_UMA _PCH_DEVFN(SIO0, 3) @@ -59,6 +77,20 @@ #define PCH_DEV_UFS0 _PCH_DEV(SIO0, 5) #define PCH_DEV_UFS1 _PCH_DEV(SIO0, 7) +#define PCH_DEV_SLOT_PSE1 0x13 +#define PCH_DEVFN_PSEGSPI0 _PCH_DEVFN(PSE1, 0) +#define PCH_DEVFN_PSEGSPI1 _PCH_DEVFN(PSE1, 1) +#define PCH_DEVFN_PSEGSPI2 _PCH_DEVFN(PSE1, 2) +#define PCH_DEVFN_PSEGSPI3 _PCH_DEVFN(PSE1, 3) +#define PCH_DEVFN_PSEGPIO0 _PCH_DEVFN(PSE1, 4) +#define PCH_DEVFN_PSEGPIO1 _PCH_DEVFN(PSE1, 5) +#define PCH_DEV_PSEGSPI0 _PCH_DEV(PSE1, 0) +#define PCH_DEV_PSEGSPI1 _PCH_DEV(PSE1, 1) +#define PCH_DEV_PSEGSPI2 _PCH_DEV(PSE1, 2) +#define PCH_DEV_PSEGSPI3 _PCH_DEV(PSE1, 3) +#define PCH_DEV_PSEGPIO0 _PCH_DEV(PSE1, 4) +#define PCH_DEV_PSEGPIO1 _PCH_DEV(PSE1, 5) + #define PCH_DEV_SLOT_XHCI 0x14 #define PCH_DEVFN_XHCI _PCH_DEVFN(XHCI, 0) #define PCH_DEVFN_USBOTG _PCH_DEVFN(XHCI, 1) @@ -89,6 +121,22 @@ #define PCH_DEVFN_SATA _PCH_DEVFN(SATA, 0) #define PCH_DEV_SATA _PCH_DEV(SATA, 0) +#define PCH_DEV_SLOT_PSE2 0x18 +#define PCH_DEVFN_PSEI2C7 _PCH_DEVFN(PSE2, 0) +#define PCH_DEVFN_PSECAN0 _PCH_DEVFN(PSE2, 1) +#define PCH_DEVFN_PSECAN1 _PCH_DEVFN(PSE2, 2) +#define PCH_DEVFN_PSEQEP0 _PCH_DEVFN(PSE2, 3) +#define PCH_DEVFN_PSEQEP1 _PCH_DEVFN(PSE2, 4) +#define PCH_DEVFN_PSEQEP2 _PCH_DEVFN(PSE2, 5) +#define PCH_DEVFN_PSEQEP3 _PCH_DEVFN(PSE2, 6) +#define PCH_DEV_PSEI2C7 _PCH_DEV(PSE2, 0) +#define PCH_DEV_PSECAN0 _PCH_DEV(PSE2, 1) +#define PCH_DEV_PSECAN1 _PCH_DEV(PSE2, 2) +#define PCH_DEV_PSEQEP0 _PCH_DEV(PSE2, 3) +#define PCH_DEV_PSEQEP1 _PCH_DEV(PSE2, 4) +#define PCH_DEV_PSEQEP2 _PCH_DEV(PSE2, 5) +#define PCH_DEV_PSEQEP3 _PCH_DEV(PSE2, 6) + #define PCH_DEV_SLOT_SIO2 0x19 #define PCH_DEVFN_I2C4 _PCH_DEVFN(SIO2, 0) #define PCH_DEVFN_I2C5 _PCH_DEVFN(SIO2, 1) @@ -103,6 +151,22 @@ #define PCH_DEV_EMMC _PCH_DEV(STORAGE, 0) #define PCH_DEV_SDCARD _PCH_DEV(STORAGE, 1) +#define PCH_DEV_SLOT_PSE3 0x1b +#define PCH_DEVFN_PSEI2C0 _PCH_DEVFN(PSE3, 0) +#define PCH_DEVFN_PSEI2C1 _PCH_DEVFN(PSE3, 1) +#define PCH_DEVFN_PSEI2C2 _PCH_DEVFN(PSE3, 2) +#define PCH_DEVFN_PSEI2C3 _PCH_DEVFN(PSE3, 3) +#define PCH_DEVFN_PSEI2C4 _PCH_DEVFN(PSE3, 4) +#define PCH_DEVFN_PSEI2C5 _PCH_DEVFN(PSE3, 5) +#define PCH_DEVFN_PSEI2C6 _PCH_DEVFN(PSE3, 6) +#define PCH_DEV_PSEI2C0 _PCH_DEV(PSE3, 0) +#define PCH_DEV_PSEI2C1 _PCH_DEV(PSE3, 1) +#define PCH_DEV_PSEI2C2 _PCH_DEV(PSE3, 2) +#define PCH_DEV_PSEI2C3 _PCH_DEV(PSE3, 3) +#define PCH_DEV_PSEI2C4 _PCH_DEV(PSE3, 4) +#define PCH_DEV_PSEI2C5 _PCH_DEV(PSE3, 5) +#define PCH_DEV_PSEI2C6 _PCH_DEV(PSE3, 6) + #define PCH_DEV_SLOT_PCIE 0x1c #define PCH_DEVFN_PCIE1 _PCH_DEVFN(PCIE, 0) #define PCH_DEVFN_PCIE2 _PCH_DEVFN(PCIE, 1) @@ -119,6 +183,24 @@ #define PCH_DEV_PCIE6 _PCH_DEV(PCIE, 5) #define PCH_DEV_PCIE7 _PCH_DEV(PCIE, 6) +#define PCH_DEV_SLOT_PSE4 0x1d +#define PCH_DEVFN_PSEIPC _PCH_DEVFN(PSE4, 0) +#define PCH_DEVFN_PSEGBE0 _PCH_DEVFN(PSE4, 1) +#define PCH_DEVFN_PSEGBE1 _PCH_DEVFN(PSE4, 2) +#define PCH_DEVFN_PSEDMA0 _PCH_DEVFN(PSE4, 3) +#define PCH_DEVFN_PSEDMA1 _PCH_DEVFN(PSE4, 4) +#define PCH_DEVFN_PSEDMA2 _PCH_DEVFN(PSE4, 5) +#define PCH_DEVFN_PSEPWM _PCH_DEVFN(PSE4, 6) +#define PCH_DEVFN_PSEADC _PCH_DEVFN(PSE4, 7) +#define PCH_DEV_PSEIPC _PCH_DEV(PSE4, 0) +#define PCH_DEV_PSEGBE0 _PCH_DEV(PSE4, 1) +#define PCH_DEV_PSEGBE1 _PCH_DEV(PSE4, 2) +#define PCH_DEV_PSEDMA0 _PCH_DEV(PSE4, 3) +#define PCH_DEV_PSEDMA1 _PCH_DEV(PSE4, 4) +#define PCH_DEV_PSEDMA2 _PCH_DEV(PSE4, 5) +#define PCH_DEV_PSEPWM _PCH_DEV(PSE4, 6) +#define PCH_DEV_PSEADC _PCH_DEV(PSE4, 7) + #define PCH_DEV_SLOT_SIO3 0x1e #define PCH_DEVFN_UART0 _PCH_DEVFN(SIO3, 0) #define PCH_DEVFN_UART1 _PCH_DEVFN(SIO3, 1) |