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-rw-r--r--src/soc/intel/tigerlake/romstage/fsp_params.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c
index 2ba276d70a..4b68cb68c5 100644
--- a/src/soc/intel/tigerlake/romstage/fsp_params.c
+++ b/src/soc/intel/tigerlake/romstage/fsp_params.c
@@ -87,6 +87,9 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
dev = pcidev_path_on_root(PCH_DEVFN_ISH);
m_cfg->PchIshEnable = is_dev_enabled(dev);
+ /* Skip GPIO configuration from FSP */
+ m_cfg->GpioOverride = 0x1;
+
/* DP port config */
m_cfg->DdiPortAConfig = config->DdiPortAConfig;
m_cfg->DdiPortBConfig = config->DdiPortBConfig;