diff options
| -rw-r--r-- | src/drivers/pc80/rtc/mc146818rtc.c | 3 | ||||
| -rw-r--r-- | src/include/pc80/mc146818rtc.h | 2 |
2 files changed, 5 insertions, 0 deletions
diff --git a/src/drivers/pc80/rtc/mc146818rtc.c b/src/drivers/pc80/rtc/mc146818rtc.c index b4ddadd4f7..1c4428a447 100644 --- a/src/drivers/pc80/rtc/mc146818rtc.c +++ b/src/drivers/pc80/rtc/mc146818rtc.c @@ -65,6 +65,9 @@ int cmos_error(void) #define RTC_CONTROL_DEFAULT (RTC_24H) #define RTC_FREQ_SELECT_DEFAULT (RTC_REF_CLCK_32KHZ | RTC_RATE_1024HZ) +_Static_assert(!CONFIG(SOC_AMD_COMMON) || !(RTC_FREQ_SELECT_DEFAULT & RTC_AMD_BANK_SELECT), + "Bank 1 should not be selected for AMD"); + static bool __cmos_init(bool invalid) { bool cmos_invalid; diff --git a/src/include/pc80/mc146818rtc.h b/src/include/pc80/mc146818rtc.h index 78184214a3..701cc73af8 100644 --- a/src/include/pc80/mc146818rtc.h +++ b/src/include/pc80/mc146818rtc.h @@ -33,6 +33,8 @@ # define RTC_REF_CLCK_4MHZ 0x00 # define RTC_REF_CLCK_1MHZ 0x10 # define RTC_REF_CLCK_32KHZ 0x20 + /* In AMD BKDG, bit 4 is DV0 bank selection. Bits 5 and 6 are reserved. */ +# define RTC_AMD_BANK_SELECT 0x10 /* 2 values for divider stage reset, others for "testing purposes only" */ # define RTC_DIV_RESET1 0x60 # define RTC_DIV_RESET2 0x70 |