diff options
| -rw-r--r-- | src/mainboard/asrock/b85m_pro4/romstage.c | 8 | ||||
| -rw-r--r-- | src/mainboard/asrock/h81m-hds/romstage.c | 8 | ||||
| -rw-r--r-- | src/mainboard/google/beltino/romstage.c | 8 | ||||
| -rw-r--r-- | src/mainboard/google/slippy/romstage.c | 8 | ||||
| -rw-r--r-- | src/mainboard/intel/baskingridge/romstage.c | 8 | ||||
| -rw-r--r-- | src/mainboard/lenovo/t440p/romstage.c | 8 | ||||
| -rw-r--r-- | src/mainboard/supermicro/x10slm-f/romstage.c | 8 | ||||
| -rw-r--r-- | src/northbridge/intel/haswell/romstage.c | 15 |
8 files changed, 15 insertions, 56 deletions
diff --git a/src/mainboard/asrock/b85m_pro4/romstage.c b/src/mainboard/asrock/b85m_pro4/romstage.c index 25f7fb2774..3a3b087706 100644 --- a/src/mainboard/asrock/b85m_pro4/romstage.c +++ b/src/mainboard/asrock/b85m_pro4/romstage.c @@ -30,14 +30,6 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) pei_data->spd_addresses[3] = 0xa6; pei_data->ec_present = 0; pei_data->gbe_enable = 1; - /* - * 0 = leave channel enabled - * 1 = disable dimm 0 on channel - * 2 = disable dimm 1 on channel - * 3 = disable dimm 0+1 on channel - */ - pei_data->dimm_channel0_disabled = 0; - pei_data->dimm_channel1_disabled = 0; pei_data->max_ddr3_freq = 1600; struct usb2_port_setting usb2_ports[MAX_USB2_PORTS] = { diff --git a/src/mainboard/asrock/h81m-hds/romstage.c b/src/mainboard/asrock/h81m-hds/romstage.c index 7c7eec3509..16f7d0d1cf 100644 --- a/src/mainboard/asrock/h81m-hds/romstage.c +++ b/src/mainboard/asrock/h81m-hds/romstage.c @@ -27,14 +27,6 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) pei_data->spd_addresses[0] = 0xa0; pei_data->spd_addresses[2] = 0xa4; pei_data->ec_present = 0; - /* - * 0 = leave channel enabled - * 1 = disable dimm 0 on channel - * 2 = disable dimm 1 on channel - * 3 = disable dimm 0+1 on channel - */ - pei_data->dimm_channel0_disabled = 2; - pei_data->dimm_channel1_disabled = 2; pei_data->max_ddr3_freq = 1600; struct usb2_port_setting usb2_ports[MAX_USB2_PORTS] = { diff --git a/src/mainboard/google/beltino/romstage.c b/src/mainboard/google/beltino/romstage.c index 015b64313f..fe3275e9d9 100644 --- a/src/mainboard/google/beltino/romstage.c +++ b/src/mainboard/google/beltino/romstage.c @@ -48,14 +48,6 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) pei_data->spd_addresses[0] = 0xa0; pei_data->spd_addresses[2] = 0xa4; pei_data->ec_present = 0; - /* - * 0 = leave channel enabled - * 1 = disable dimm 0 on channel - * 2 = disable dimm 1 on channel - * 3 = disable dimm 0+1 on channel - */ - pei_data->dimm_channel0_disabled = 2; - pei_data->dimm_channel1_disabled = 2; /* Enable 2x refresh mode */ pei_data->ddr_refresh_2x = 1; pei_data->dq_pins_interleaved = 1; diff --git a/src/mainboard/google/slippy/romstage.c b/src/mainboard/google/slippy/romstage.c index 7e1520dbed..ea95853663 100644 --- a/src/mainboard/google/slippy/romstage.c +++ b/src/mainboard/google/slippy/romstage.c @@ -48,14 +48,6 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) pei_data->spd_addresses[0] = 0xff; pei_data->spd_addresses[2] = 0xff; pei_data->ec_present = 1; - /* - * 0 = leave channel enabled - * 1 = disable dimm 0 on channel - * 2 = disable dimm 1 on channel - * 3 = disable dimm 0+1 on channel - */ - pei_data->dimm_channel0_disabled = 2; - pei_data->dimm_channel1_disabled = 2; pei_data->max_ddr3_freq = 1600; pei_data->usb_xhci_on_resume = 1; diff --git a/src/mainboard/intel/baskingridge/romstage.c b/src/mainboard/intel/baskingridge/romstage.c index 6bb09a56bc..a156095bef 100644 --- a/src/mainboard/intel/baskingridge/romstage.c +++ b/src/mainboard/intel/baskingridge/romstage.c @@ -52,14 +52,6 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) pei_data->spd_addresses[2] = 0xa4; pei_data->spd_addresses[3] = 0xa6; pei_data->ec_present = 0; - /* - * 0 = leave channel enabled - * 1 = disable dimm 0 on channel - * 2 = disable dimm 1 on channel - * 3 = disable dimm 0+1 on channel - */ - pei_data->dimm_channel0_disabled = 0; - pei_data->dimm_channel1_disabled = 0; pei_data->max_ddr3_freq = 1600; struct usb2_port_setting usb2_ports[MAX_USB2_PORTS] = { diff --git a/src/mainboard/lenovo/t440p/romstage.c b/src/mainboard/lenovo/t440p/romstage.c index 4f49e78ee0..53088d6826 100644 --- a/src/mainboard/lenovo/t440p/romstage.c +++ b/src/mainboard/lenovo/t440p/romstage.c @@ -50,14 +50,6 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) pei_data->spd_addresses[2] = 0xa2; pei_data->ec_present = 1; pei_data->gbe_enable = 1; - /* - * 0 = leave channel enabled - * 1 = disable dimm 0 on channel - * 2 = disable dimm 1 on channel - * 3 = disable dimm 0+1 on channel - */ - pei_data->dimm_channel0_disabled = 2; - pei_data->dimm_channel1_disabled = 2; pei_data->max_ddr3_freq = 1600; struct usb2_port_setting usb2_ports[MAX_USB2_PORTS] = { diff --git a/src/mainboard/supermicro/x10slm-f/romstage.c b/src/mainboard/supermicro/x10slm-f/romstage.c index c1631b35e4..ce8f888d13 100644 --- a/src/mainboard/supermicro/x10slm-f/romstage.c +++ b/src/mainboard/supermicro/x10slm-f/romstage.c @@ -28,14 +28,6 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) pei_data->spd_addresses[2] = 0xa4; pei_data->spd_addresses[3] = 0xa6; pei_data->ec_present = 0; - /* - * 0 = leave channel enabled - * 1 = disable dimm 0 on channel - * 2 = disable dimm 1 on channel - * 3 = disable dimm 0+1 on channel - */ - pei_data->dimm_channel0_disabled = 0; - pei_data->dimm_channel1_disabled = 0; pei_data->ddr_refresh_2x = 1; pei_data->max_ddr3_freq = 1600; diff --git a/src/northbridge/intel/haswell/romstage.c b/src/northbridge/intel/haswell/romstage.c index ee211beab1..7c27827921 100644 --- a/src/northbridge/intel/haswell/romstage.c +++ b/src/northbridge/intel/haswell/romstage.c @@ -23,6 +23,17 @@ void __weak mb_late_romstage_setup(void) { } +/* + * 0 = leave channel enabled + * 1 = disable dimm 0 on channel + * 2 = disable dimm 1 on channel + * 3 = disable dimm 0+1 on channel + */ +static int make_channel_disabled_mask(const struct pei_data *pd, int ch) +{ + return (!pd->spd_addresses[ch + ch] << 0) | (!pd->spd_addresses[ch + ch + 1] << 1); +} + /* The romstage entry point for this platform is not mainboard-specific, hence the name */ void mainboard_romstage_entry(void) { @@ -73,6 +84,10 @@ void mainboard_romstage_entry(void) /* MRC has hardcoded assumptions of 2 meaning S3 wake. Normalize it here. */ pei_data.boot_mode = wake_from_s3 ? 2 : 0; + /* Calculate unimplemented DIMM slots for each channel */ + pei_data.dimm_channel0_disabled = make_channel_disabled_mask(&pei_data, 0); + pei_data.dimm_channel1_disabled = make_channel_disabled_mask(&pei_data, 1); + timestamp_add_now(TS_BEFORE_INITRAM); report_platform_info(); |