diff options
-rw-r--r-- | src/device/Kconfig | 47 | ||||
-rw-r--r-- | src/mainboard/asus/kfsn4-dre/Kconfig | 4 | ||||
-rw-r--r-- | src/mainboard/asus/kfsn4-dre_k8/Kconfig | 4 | ||||
-rw-r--r-- | src/mainboard/google/slippy/Kconfig | 1 | ||||
-rw-r--r-- | src/mainboard/sapphire/pureplatinumh61/Kconfig | 1 | ||||
-rw-r--r-- | src/northbridge/intel/haswell/gma.c | 2 | ||||
-rw-r--r-- | src/northbridge/intel/nehalem/gma.c | 62 | ||||
-rw-r--r-- | src/northbridge/intel/pineview/Kconfig | 5 | ||||
-rw-r--r-- | src/northbridge/intel/sandybridge/Kconfig | 4 | ||||
-rw-r--r-- | src/northbridge/intel/sandybridge/gma.c | 3 |
10 files changed, 64 insertions, 69 deletions
diff --git a/src/device/Kconfig b/src/device/Kconfig index 841f2249b2..0637c699f7 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -42,39 +42,36 @@ config MAINBOARD_HAS_NATIVE_VGA_INIT config MAINBOARD_FORCE_NATIVE_VGA_INIT def_bool n depends on MAINBOARD_HAS_NATIVE_VGA_INIT || MAINBOARD_HAS_LIBGFXINIT - select MAINBOARD_DO_NATIVE_VGA_INIT help Selected by mainboards / chipsets whose graphics driver can't or shouldn't be disabled. -config MAINBOARD_DO_NATIVE_VGA_INIT - bool "Use native graphics initialization" - depends on MAINBOARD_HAS_NATIVE_VGA_INIT - default n - help - Some mainboards, such as the Google Link, allow initializing the display - without the need of a binary only VGA OPROM. Enabling this option may be - faster, but also lacks flexibility in setting modes. - - If unsure, say N. - config MAINBOARD_HAS_LIBGFXINIT def_bool n - select MAINBOARD_HAS_NATIVE_VGA_INIT help Selected by mainboards that implement support for `libgfxinit`. Usually this requires a list of ports to be probed for displays. +choice + prompt "Graphics initialization" + default NO_GFX_INIT if VGA_BIOS && PAYLOAD_SEABIOS + default VGA_ROM_RUN if VGA_BIOS + +config MAINBOARD_DO_NATIVE_VGA_INIT + bool "Use native graphics init" + depends on MAINBOARD_HAS_NATIVE_VGA_INIT + help + Some mainboards, such as the Google Link, allow initializing the + display without the need of a binary only VGA OPROM. Enabling this + option may be faster, but also lacks flexibility in setting modes. + config MAINBOARD_USE_LIBGFXINIT - bool "Use libgfxinit for native graphics initialization" - depends on MAINBOARD_DO_NATIVE_VGA_INIT + bool "Use libgfxinit" depends on MAINBOARD_HAS_LIBGFXINIT select HAVE_VGA_TEXT_FRAMEBUFFER select HAVE_LINEAR_FRAMEBUFFER select RAMSTAGE_LIBHWBASE select VGA if VGA_TEXT_FRAMEBUFFER - select NO_EDID_FILL_FB - default n help Use the SPARK library `libgfxinit` for the native graphics initialization. This requires an Ada toolchain. @@ -82,12 +79,10 @@ config MAINBOARD_USE_LIBGFXINIT # TODO: Explain differences (if any) for onboard cards. config VGA_ROM_RUN bool "Run VGA Option ROMs" - default n if PAYLOAD_SEABIOS - default y if !PAYLOAD_SEABIOS - depends on PCI && !MAINBOARD_DO_NATIVE_VGA_INIT + depends on PCI && !MAINBOARD_FORCE_NATIVE_VGA_INIT select HAVE_VGA_TEXT_FRAMEBUFFER help - Execute VGA Option ROMs in coreboot if found. This is required + Execute VGA Option ROMs in coreboot if found. This can be used to enable PCI/AGP/PCI-E video cards when not using a SeaBIOS payload. @@ -95,7 +90,15 @@ config VGA_ROM_RUN more complete BIOS interrupt services available than coreboot, which some option ROMs require in order to function correctly. - If unsure, say N when using SeaBIOS as payload, Y otherwise. +config NO_GFX_INIT + bool "None" + depends on !MAINBOARD_FORCE_NATIVE_VGA_INIT + help + Select this to not perform any graphics initialization in + coreboot. This is useful if the payload (e.g. SeaBIOS) can + initialize graphics or if pre-boot graphics are not required. + +endchoice config S3_VGA_ROM_RUN bool "Re-run VGA Option ROMs on S3 resume" diff --git a/src/mainboard/asus/kfsn4-dre/Kconfig b/src/mainboard/asus/kfsn4-dre/Kconfig index 0920056841..3e9f3f35e3 100644 --- a/src/mainboard/asus/kfsn4-dre/Kconfig +++ b/src/mainboard/asus/kfsn4-dre/Kconfig @@ -81,10 +81,6 @@ config ONBOARD_VGA_IS_PRIMARY bool default y -config MAINBOARD_DO_NATIVE_VGA_INIT - bool - default y - config MAINBOARD_POWER_ON_AFTER_POWER_FAIL bool default y diff --git a/src/mainboard/asus/kfsn4-dre_k8/Kconfig b/src/mainboard/asus/kfsn4-dre_k8/Kconfig index 8bd2146d95..0d13a4ece4 100644 --- a/src/mainboard/asus/kfsn4-dre_k8/Kconfig +++ b/src/mainboard/asus/kfsn4-dre_k8/Kconfig @@ -87,10 +87,6 @@ config ONBOARD_VGA_IS_PRIMARY bool default y -config MAINBOARD_DO_NATIVE_VGA_INIT - bool - default y - config MAINBOARD_POWER_ON_AFTER_POWER_FAIL bool default y diff --git a/src/mainboard/google/slippy/Kconfig b/src/mainboard/google/slippy/Kconfig index 1d889df97e..e24e2f74f7 100644 --- a/src/mainboard/google/slippy/Kconfig +++ b/src/mainboard/google/slippy/Kconfig @@ -15,7 +15,6 @@ config BOARD_GOOGLE_BASEBOARD_SLIPPY select MAINBOARD_HAS_LPC_TPM select INTEL_INT15 select MAINBOARD_HAS_LIBGFXINIT - select MAINBOARD_USE_LIBGFXINIT if MAINBOARD_DO_NATIVE_VGA_INIT if BOARD_GOOGLE_BASEBOARD_SLIPPY diff --git a/src/mainboard/sapphire/pureplatinumh61/Kconfig b/src/mainboard/sapphire/pureplatinumh61/Kconfig index f9458a62a3..6ade9b5d29 100644 --- a/src/mainboard/sapphire/pureplatinumh61/Kconfig +++ b/src/mainboard/sapphire/pureplatinumh61/Kconfig @@ -14,7 +14,6 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_CMOS_DEFAULT select HAVE_ACPI_RESUME select MAINBOARD_HAS_LIBGFXINIT - select MAINBOARD_USE_LIBGFXINIT if MAINBOARD_DO_NATIVE_VGA_INIT select INTEL_INT15 select UDELAY_TSC select SERIRQ_CONTINUOUS_MODE diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index a7478de128..1379539b4f 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -443,7 +443,7 @@ static void gma_func0_init(struct device *dev) /* Pre panel init */ gma_setup_panel(dev); - if (IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) { + if (IS_ENABLED(CONFIG_MAINBOARD_USE_LIBGFXINIT)) { printk(BIOS_SPEW, "NATIVE graphics, run native enable\n"); physbase = pci_read_config32(dev, 0x5c) & ~0xf; gma_gfxinit(gtt_res->base, linearfb_res->base, diff --git a/src/northbridge/intel/nehalem/gma.c b/src/northbridge/intel/nehalem/gma.c index 0af8d6c63a..43ca4b661a 100644 --- a/src/northbridge/intel/nehalem/gma.c +++ b/src/northbridge/intel/nehalem/gma.c @@ -1008,38 +1008,40 @@ static void gma_func0_init(struct device *dev) /* Init graphics power management */ gma_pm_init_pre_vbios(dev); -#if !CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT - /* PCI Init, will run VBIOS */ - pci_dev_init(dev); -#else - u32 physbase; - struct northbridge_intel_nehalem_config *conf = dev->chip_info; - struct resource *lfb_res; - struct resource *pio_res; - - lfb_res = find_resource(dev, PCI_BASE_ADDRESS_2); - pio_res = find_resource(dev, PCI_BASE_ADDRESS_4); - - physbase = pci_read_config32(dev, 0x5c) & ~0xf; - - if (gtt_res && gtt_res->base && physbase && pio_res && pio_res->base - && lfb_res && lfb_res->base) { - printk(BIOS_SPEW, "Initializing VGA without OPROM. MMIO 0x%llx\n", - gtt_res->base); - if (IS_ENABLED(CONFIG_MAINBOARD_USE_LIBGFXINIT)) { - int lightup_ok; - gma_gfxinit(gtt_res->base, lfb_res->base, - physbase, &lightup_ok); - } else { - intel_gma_init(conf, res2mmio(gtt_res, 0, 0), physbase, - pio_res->base, lfb_res->base); + if (IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) || + IS_ENABLED(CONFIG_MAINBOARD_USE_LIBGFXINIT)) { + u32 physbase; + struct northbridge_intel_nehalem_config *conf = dev->chip_info; + struct resource *lfb_res; + struct resource *pio_res; + + lfb_res = find_resource(dev, PCI_BASE_ADDRESS_2); + pio_res = find_resource(dev, PCI_BASE_ADDRESS_4); + + physbase = pci_read_config32(dev, 0x5c) & ~0xf; + + if (gtt_res && gtt_res->base && physbase && + pio_res && pio_res->base && lfb_res && lfb_res->base) { + printk(BIOS_SPEW, + "Initializing VGA without OPROM. MMIO 0x%llx\n", + gtt_res->base); + if (IS_ENABLED(CONFIG_MAINBOARD_USE_LIBGFXINIT)) { + int lightup_ok; + gma_gfxinit(gtt_res->base, lfb_res->base, + physbase, &lightup_ok); + } else { + intel_gma_init(conf, res2mmio(gtt_res, 0, 0), + physbase, pio_res->base, lfb_res->base); + } } - } - - /* Linux relies on VBT for panel info. */ - generate_fake_intel_oprom(&conf->gfx, dev, "$VBT IRONLAKE-MOBILE"); -#endif + /* Linux relies on VBT for panel info. */ + generate_fake_intel_oprom(&conf->gfx, dev, + "$VBT IRONLAKE-MOBILE"); + } else { + /* PCI Init, will run VBIOS */ + pci_dev_init(dev); + } /* Post VBIOS init */ gma_pm_init_post_vbios(dev); diff --git a/src/northbridge/intel/pineview/Kconfig b/src/northbridge/intel/pineview/Kconfig index cf659efb1a..1af8d3cb4c 100644 --- a/src/northbridge/intel/pineview/Kconfig +++ b/src/northbridge/intel/pineview/Kconfig @@ -26,12 +26,9 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy select VGA select MAINBOARD_HAS_NATIVE_VGA_INIT select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT + select INTEL_EDID if MAINBOARD_DO_NATIVE_VGA_INIT select RELOCATABLE_RAMSTAGE -config MAINBOARD_DO_NATIVE_VGA_INIT - def_bool y - select INTEL_EDID - config BOOTBLOCK_NORTHBRIDGE_INIT string default "northbridge/intel/pineview/bootblock.c" diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index ad1ceae531..b52807cc94 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -59,7 +59,9 @@ config SANDYBRIDGE_IVYBRIDGE_LVDS select VGA select MAINBOARD_HAS_NATIVE_VGA_INIT -config MAINBOARD_DO_NATIVE_VGA_INIT +config IF_NATIVE_VGA_INIT + def_bool y + depends on MAINBOARD_DO_NATIVE_VGA_INIT select VGA select INTEL_EDID select HAVE_LINEAR_FRAMEBUFFER diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c index 868a961fb8..bc64fe695b 100644 --- a/src/northbridge/intel/sandybridge/gma.c +++ b/src/northbridge/intel/sandybridge/gma.c @@ -595,7 +595,8 @@ static void gma_func0_init(struct device *dev) /* Post VBIOS init */ gma_pm_init_post_vbios(dev); - if (IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) { + if (IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) || + IS_ENABLED(CONFIG_MAINBOARD_USE_LIBGFXINIT)) { /* This should probably run before post VBIOS init. */ printk(BIOS_SPEW, "Initializing VGA without OPROM.\n"); u8 *mmiobase; |