diff options
| -rw-r--r-- | src/mainboard/google/brya/variants/baseboard/devicetree.cb | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/baseboard/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/devicetree.cb index b6b49dc361..c992f4fd2f 100644 --- a/src/mainboard/google/brya/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/devicetree.cb @@ -3,6 +3,12 @@ chip soc/intel/alderlake device lapic 0 on end end + # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f + register "gen1_dec" = "0x00fc0801" + register "gen2_dec" = "0x000c0201" + # EC memory map range is 0x900-0x9ff + register "gen3_dec" = "0x00fc0901" + # This disabled autonomous GPIO power management, otherwise # old cr50 FW only supports short pulses; need to clarify # the minimum PCH IRQ pulse width with Intel, b/180111628 |