diff options
| -rw-r--r-- | src/mainboard/intel/adlrvp/chromeos.fmd | 12 |
1 files changed, 9 insertions, 3 deletions
diff --git a/src/mainboard/intel/adlrvp/chromeos.fmd b/src/mainboard/intel/adlrvp/chromeos.fmd index 28cda245e4..ef3320f746 100644 --- a/src/mainboard/intel/adlrvp/chromeos.fmd +++ b/src/mainboard/intel/adlrvp/chromeos.fmd @@ -1,14 +1,20 @@ FLASH 32M { SI_ALL 6M { SI_DESC 4K - SI_ME + SI_ME { + CSE_LAYOUT 8K + CSE_RO 1588K + CSE_DATA 512K + # 64-KiB aligned to optimize RW erases during CSE update. + CSE_RW 4032K + } } SI_BIOS 26M { RW_SECTION_A 8M { VBLOCK_A 64K FW_MAIN_A(CBFS) RW_FWID_A 64 - ME_RW_A(CBFS) 3M + ME_RW_A(CBFS) 4032K } RW_LEGACY(CBFS) 1M RW_MISC 1M { @@ -32,7 +38,7 @@ FLASH 32M { VBLOCK_B 64K FW_MAIN_B(CBFS) RW_FWID_B 64 - ME_RW_B(CBFS) 3M + ME_RW_B(CBFS) 4032K } # Make WP_RO region align with SPI vendor # memory protected range specification. |